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? 2000 microchip technology inc. preliminary ds41124c-page 1 devices included in this data sheet: microcontroller core features: ? high-performance risc cpu only 35 single word instructions all single cycle instructions except for program branches which are two cycle interrupt capability (up to 12 internal/external interrupt sources) eight level deep hardware stack direct, indirect and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation brown-out detection circuitry for brown-out reset (bor) programmable code-protection power saving sleep mode selectable oscillator options - ec - external clock (24 mhz) - e4 - external clock with pll (6 mhz) - hs - crystal/resonator (24 mhz) - h4 - crystal/resonator with pll (6 mhz) processor clock of 24 mhz derived from 6 mhz crystal or resonator fully static low-power, high-speed cmos in-circuit serial programming ? (icsp) operating voltage range - 4.35 to 5.25v high sink/source current 25/25 ma wide temperature range - industrial (-40 c - 85 c) low-power consumption: - ~ 16 ma @ 5v, 24 mhz -100 a typical standby current pin diagrams peripheral features: universal serial bus (usb 1.1) - soft attach/detach 64 bytes of usb dual port ram 22 (pic16c745) or 33 (pic16c765) i/o pins - individual direction control - 1 high voltage open drain (ra4) - 8 portb pins with: - interrupt-on-change control (rb<7:4> only) - weak pull-up control - 3 pins dedicated to usb timer0: 8-bit timer/counter with 8-bit prescaler timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler 2 capture, compare and pwm modules - capture is 16-bit, max. resolution is 10.4 ns - compare is 16-bit, max. resolution is 167 ns - pwm maximum resolution is 10-bit 8-bit multi-channel analog-to-digital converter universal synchronous asynchronous receiver transmitter (usart/sci) parallel slave port (psp) 8-bits wide, with exter- nal rd , wr and cs controls (pic16c765 only) pic16c745 pic16c765 device memory pins a/d resolution a/d channels program x14 data x8 pic16c745 8k 256 28 8 5 pic16c765 8k 256 40 8 8 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4 vss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 v usb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd vss rc7/rx/dt rc6/tx/ck d+ d- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c745 28-pin dip, soic pic16c745/765 8-bit cmos microcontrollers with usb 745cov.book page 1 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 2 preliminary ? 2000 microchip technology inc. rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/an4 re0/rd/an5 re1/wr/an6 re2/cs/an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki nc ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck d+ d- rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 v usb rc2/ccp1 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 pic16c765 44-pin plcc rc1/t1osi/ccp2 nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs/an7 re1/wr/an6 re0/rd/an5 ra5/an4 ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck d+ d- rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 v usb rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 pic16c765 44-pin tqfp rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck d+ d- rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4 re0/rd/an5 re1/wr/an6 re2/cs/an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 v usb rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c765 40-pin dip key features picmicro tm mid-range reference manual (ds33023) pic16c745 pic16c765 operating frequency 6 mhz or 24 mhz 6 mhz or 24 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) program memory (14-bit words) 8k 8k data memory (bytes) 256 256 dual port ram 64 64 interrupt sources 11 12 i/o ports 22 (ports a, b, c) 33 (ports a, b, c, d, e) timers 3 3 capture/compare/pwm modules 2 2 analog-to-digital converter module 5 channel x 8 bit 8 channel x 8 bit parallel slave port ? yes serial communication usb, usart/sci usb, usart/sci brown-out detect reset yes yes 745cov.book page 2 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 3 pic16c745/765 table of contents 1.0 general description ......................................................................................................... ..................................... 5 2.0 pic16c745/765 device varieties .............................................................................................. ........................... 7 3.0 architectural overview ...................................................................................................... .................................... 9 4.0 memory organization......................................................................................................... ................................. 15 5.0 i/o ports................................................................................................................... ........................................... 31 6.0 timer0 module ............................................................................................................... ..................................... 43 7.0 timer1 module ............................................................................................................... ..................................... 45 8.0 timer2 module ............................................................................................................... ..................................... 49 9.0 capture/compare/pwm modules ................................................................................................. ...................... 51 10.0 universal serial bus....................................................................................................... ..................................... 57 11.0 universal synchronous asynchronous receiver transmitter (usart) ............................................................ .77 12.0 analog-to-digital converter (a/d) module ................................................................................... ....................... 91 13.0 special features of the cpu ................................................................................................ .............................. 99 14.0 instruction set summary.................................................................................................... ............................... 113 15.0 development support ........................................................................................................ ............................... 121 16.0 electrical characteristics................................................................................................. .................................. 127 17.0 dc and ac characteristics graphs and tables ................................................................................ ............... 145 18.0 packaging information ...................................................................................................... ................................ 147 index .......................................................................................................................... ................................................ 157 on-line support................................................................................................................ .......................................... 161 reader response ................................................................................................................ ....................................... 162 product identification system .................................................................................................. ................................... 163 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: fill out and mail in the reader response form in the back of this data sheet. e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document. 745cov.book page 3 wednesday, august 2, 2000 8:24 am
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? 2000 microchip technology inc. preliminary ds41124c-page 5 pic16c745/765 1.0 general description the pic16c745/765 devices are low cost, high-perfor- mance, cmos, fully-static, 8-bit microcontrollers in the pic16cxx mid-range family. all picmicro ? microcontrollers employ an advanced risc architecture. the pic16c745/765 microcontrol- ler family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. a total of 35 instructions (reduced instruction set) are available. additionally, a large reg- ister set gives some of the architectural innovations used to achieve a very high performance. the pic16c745 device has 22 i/o pins. the pic16c765 device has 33 i/o pins. each device has 256 bytes of ram. in addition, several peripheral fea- tures are available including: three timer/counters, two capture/compare/pwm modules and two serial ports. the universal serial bus (usb 1.1) low speed periph- eral provides bus communications. the universal synchronous asynchronous receiver transmitter (usart) is also known as the serial communications interface or sci. also, a 5-channel high-speed 8-bit a/d is provided on the pic16c745, while the pic16c765 offers 8 channels. the 8-bit resolution is ideally suited for applications requiring a low cost ana- log interface (e.g., thermostat control, pressure sens- ing, etc.). the pic16c745/765 devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power con- sumption. there are 4 oscillator options, of which ec is for the external regulated clock source, e4 is for the external regulated clock source with the pll enabled, hs is for the high speed crystals/resonators and h4 is for high speed crystals/resonators with the pll enabled. the sleep (power-down) feature provides a power-saving mode. the user can wake-up the chip from sleep through several external and internal interrupts and resets. a highly reliable watchdog timer (wdt), with a dedi- cated on-chip rc oscillator, provides protection against software lock-up, and also provides one way of waking the device from sleep. a uv erasable cerdip packaged version is ideal for code development, while the cost-effective one-time- programmable (otp) version is suitable for production in any volume. the pic16c745/765 devices fit nicely in many applica- tions ranging from security and remote sensors to appli- ance controls and automotives. the eprom technology makes customization of application pro- grams (data loggers, industrial controls, ups) extremely fast and convenient. the small footprint pack- ages make this microcontroller series perfect for all applications with space limitations. low-cost, low- power, high-performance, ease of use and i/o flexib ility make the pic16c745/765 devices very versatile, even in areas where no microcontroller use has been consid- ered before (e.g., timer functions, serial communication, capture and compare, pwm functions and coprocessor applications). 1.1 family and upward compatibility users familiar with the pic16c5x microcontroller fam- ily will realize that this is an enhanced version of the pic16c5x architecture. code written for the pic16c5x can be easily ported to the pic16c745/765 family of devices. 1.2 development support picmicro ? devices are supported by the complete line of microchip development tools. please refer to section 15.0 for more details about microchip ? s development tools. 745cov.book page 5 wednesday, august 2, 2000 8:24 am
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? 2000 microchip technology inc. preliminary ds41124c-page 7 pic16c745/765 2.0 pic16c745/765 device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c745/765 product identification system section at the end of this data sheet. when placing orders, please use that page of the data sheet to specify the correct part number. 2.1 uv erasable devices the uv erasable version, offered in windowed cerdip packages, is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the supported oscillator modes. microchip ? s picstart ? plus and pro mate ? ii programmers both support programming of the pic16c745/765. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must also be programmed. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and configuration options already programmed by the factory. certain code and prototype verification procedures apply before produc- tion shipments are available. please contact your local microchip technology sales office for more details. 2.4 serialized quick-turnaround production (sqtp sm ) devices microchip offers a unique programming service where a few user-defined locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry-code, password or id number. 745cov.book page 7 wednesday, august 2, 2000 8:24 am
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? 2000 microchip technology inc. preliminary ds41124c-page 9 pic16c745/765 3.0 architectural overview the high performance of the pic16c745/765 family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16c745/765 uses a harvard architecture, in which program and data are accessed from separate memories using separate buses. this improves band- width over traditional von neumann architecture in which program and data are fetched from the same memory using the same bus. separating program and data buses further allows instructions to be sized differ- ently than the 8-bit wide data word. instruction opcodes are 14-bits wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions (example 3-1). consequently, most instructions execute in a single cycle (166.6667 ns @ 24 mhz) except for program branches. the pic16c745/765 can directly or indirectly address its register files or data memory. all special function registers, including the program counter, are mapped in the data memory. the pic16c745/765 has an orthog- onal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ? special optimal situations ? make programming with the pic16c745/765 simple yet efficient. in addition, the learning curve is reduced significantly. pic16c745/765 devices contain an 8-bit alu and working register. the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between the data in the working register and any regis- ter file. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a file register or an immediate con- stant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. device memory pins a/d resolution a/d channels program x14 data x8 pic16c745 8k 256 28 8 5 pic16c765 8k 256 40 8 8 745cov.book page 9 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 10 preliminary ? 2000 microchip technology inc. figure 3-1: pic16c745/765 block diagram 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13 bit) direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/ osc2/ mclr v dd , v ss porta portb portc portd porte ra4/t0cki ra5/an4 rb0/int rb<7:1> rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 v usb d- d+ rc6/tx/ck rc7/rx/dt rd3:0/psp3:0 (2) re0/an5/rd (2) re1/an6/wr (2) 8 8 brown-out reset note 1: higher order bits are from the status register. 2: not available on pic16c745. usart ccp1 8-bit a/d timer0 timer1 timer2 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 parallel slave port (2) 8 3 rd4/psp4 (2) rd5/psp5 (2) rd6/psp6 (2) rd7/psp7 (2) usb clkout clkin ccp2 xcvr ram file registers 256 x 8 dual port eprom program memory 8k x 14 ram 64 x 8 x4 pll re2/an7/cs (2) 745cov.book page 10 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 11 pic16c745/765 table 3-1: pic16c745/765 pinout description name function input type output type description mclr /v pp mclr st ? master clear v pp power ? programming voltage osc1/clkin osc1 xtal ? crystal/resonator clkin st ? external clock input osc2/clkout osc2 ? xtal crystal/resonator clkout ? cmos internal clock (f int /4) output ra0/an0 ra0 st cmos bi-directional i/o an0 an ? a/d input ra1/an1 ra1 st cmos bi-directional i/o an1 an ? a/d input ra2/an2 ra2 st cmos bi-directional i/o an2 an ? a/d input ra3/an3/v ref ra3 st cmos bi-directional i/o an3 an ? a/d input v ref an ? a/d positive reference ra4/t0cki ra4 st od bi-directional i/o t0cki st ? timer 0 clock input ra5/an4 ra5 st bi-directional i/o an4 an ? a/d input rb0/int rb0 ttl cmos bi-directional i/o (1) int st ? interrupt rb1 rb1 ttl cmos bi-directional i/o (1) rb2 rb2 ttl cmos bi-directional i/o (1) rb3 rb3 ttl cmos bi-directional i/o (1) rb4 rb4 ttl cmos bi-directional i/o with interrupt-on-change (1) rb5 rb5 ttl cmos bi-directional i/o with interrupt-on-change (1) rb6/icspc rb6 ttl cmos bi-directional i/o with interrupt-on-change (1) icspc st in-circuit serial programming clock input rb7/icspd rb7 ttl cmos bi-directional i/o with interrupt-on-change (1) icspd st cmos in-circuit serial programming data i/o rc0/t1oso/t1cki rc0 st cmos bi-directional i/o t1oso ? xtal t1 oscillator output t1cki st ? t1 clock input rc1/t1osi/ccp2 (1) rc1 st cmos bi-directional i/o t1osi xtal ? t1 oscillator input ccp2 capture in/compare out/pwm out 2 rc2/ccp1 rc2 st cmos bi-directional i/o ccp1 capture in/compare out/pwm out 1 v usb v usb power regulator output voltage d- d- usb usb usb differential bus d+ d+ usb usb usb differential bus legend: od = open drain, st = schmitt trigger note 1: weak pull-ups. port b pull-ups are byte wide programmable. 2: pic16c765 only. 745cov.book page 11 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 12 preliminary ? 2000 microchip technology inc. rc6/tx/ck rc6 st cmos bi-directional i/o tx ? cmos usart async transmit ck st cmos usart master out/slave in clock rc7/rx/dt rc7 st cmos bi-directional i/o rx st ? usart async receive dt st cmos usart data i/o rd0/psp0 rd0 ttl cmos bi-directional i/o (2) psp0 ttl ? parallel slave port data input (2) rd1/psp1 rd1 ttl cmos bi-directional i/o (2) psp1 ttl ? parallel slave port data input (2) rd2/psp2 rd2 ttl cmos bi-directional i/o (2) psp2 ttl ? parallel slave port data input (2) rd3/psp3 rd3 ttl cmos bi-directional i/o (2) psp3 ttl ? parallel slave port data input (2) rd4/psp4 rd4 ttl cmos bi-directional i/o (2) psp4 ttl ? parallel slave port data input (2) rd5/psp5 rd5 ttl cmos bi-directional i/o (2) psp5 ttl ? parallel slave port data input (2) rd6/psp6 rd6 ttl cmos bi-directional i/o (2) psp6 ttl ? parallel slave port data input (2) rd7/psp7 rd7 ttl cmos bi-directional i/o (2) psp7 ttl ? parallel slave port data input (2) re0/rd /an5 re0 st cmos bi-directional i/o (2) rd ttl ? parallel slave port control input (2) an5 an ? a/d input (2) re1/wr /an6 re1 st cmos bi-directional i/o (2) wr ttl ? parallel slave port control input (2) an6 an ? a/d input (2) re2/cs /an7 re2 st cmos bi-directional i/o (2) cs ttl ? parallel slave port data input (2) an7 an ? a/d input (2) v dd v dd power ? power v ss v ss power ? ground table 3-1: pic16c745/765 pinout description (continued) name function input type output type description legend: od = open drain, st = schmitt trigger note 1: weak pull-ups. port b pull-ups are byte wide programmable. 2: pic16c765 only. 745cov.book page 12 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 13 pic16c745/765 3.1 clocking scheme/instruction cycle the clock input feeds either an on-chip pll, or directly drives (f int ). the clock output from either the pll or direct drive (f int ) is internally divided by four to gener- ate four non-overlapping quadrature clocks namely, q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruc- tion register in q4. the instruction is decoded and exe- cuted during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2. 3.2 instruction flow/pipelining an ? instruction cycle ? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ? instruction register" (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 f int q1 q2 q3 q4 pc osc2/clkout (ec mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock note: all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ? flushed ? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1 745cov.book page 13 wednesday, august 2, 2000 8:24 am
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? 2000 microchip technology inc. preliminary ds41124c-page 15 pic16c745/765 4.0 memory organization 4.1 program memory organization the pic16c745/765 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. all devices covered by this data sheet have 8k x 14 bits of program memory. the address range is 0000h - 1fffh for all devices. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 4-1: pic16c745/765 program memory map and stack 4.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers (gpr) and the special function registers (sfr). bits rp1 and rp0 are the bank select bits. rp<1:0> (status<6:5>) = 00 bank0 = 01 bank1 = 10 bank2 = 11 bank3 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the sfrs. above the sfrs are gprs, implemented as static ram. all implemented banks contain sfrs. some ? high use ? sfrs from one bank may be mirrored in another bank for code reduction and quicker access. 4.2.1 general purpose register file the register file can be accessed either directly or indi- rectly through the file select register (fsr) (section 4.5). pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw stack level 2 program memory page 0 page 1 07ffh 0800h 0fffh 1000h page 2 1800h 17ffh page 3 1fffh 745cov.book page 15 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 16 preliminary ? 2000 microchip technology inc. figure 4-2: data memory map for pic16c745/765 bank 0 file address bank 1 file address bank 2 file address bank 3 file address indirect addr. (*) 00h indirect addr. (*) 80h indirect addr. (*) 100h indirect addr. (*) 180h tmr0 01h option_reg 81h tmr0 101h option_reg 181h pcl 02h pcl 82h pcl 102h pcl 182h status 03h status 83h status 103h status 183h fsr 04h fsr 84h fsr 104h fsr 184h porta 05h trisa 85h 105h 185h portb 06h trisb 86h portb 106h trisb 186h portc 07h trisc 87h 107h 187h portd (2) 08h trisd (2) 88h 108h 188h porte (2) 09h trise (2) 89h 109h 189h pclath 0ah pclath 8ah pclath 10ah pclath 18ah intcon 0bh intcon 8bh intcon 10bh intcon 18bh pir1 0ch pie1 8ch 10ch 18ch pir2 0dh pie2 8dh 10dh 18dh tmr1l 0eh pcon 8eh 10eh 18eh tmr1h 0fh 8fh 10fh 18fh t1con 10h 90h 110h uir 190h tmr2 11h 91h 111h uie 191h t2con 12h pr2 92h 112h ueir 192h 13h 93h 113h ueie 193h 14h 94h 114h ustat 194h ccpr1l 15h 95h 115h uctrl 195h ccpr1h 16h 96h 116h uaddr 196h ccp1con 17h 97h 117h uswstat (1) 197h rcsta 18h txsta 98h 118h uep0 198h txreg 19h spbrg 99h 119h uep1 199h rcreg 1ah 9ah 11ah uep2 19ah ccpr2l 1bh 9bh 11bh 19bh (1) ccpr2h 1ch 9ch 11ch 19ch (1) ccp2con 1dh 9dh 11dh 19dh (1) adres 1eh 9eh 11eh 19eh (1) adcon0 1fh adcon1 9fh 11fh 19fh (1) general purpose register 96 bytes 20h general purpose register 80 bytes a0h general purpose register 80 bytes 120h usb dual port memory 64 bytes 1a0h 1dfh 1e0h efh 16fh 1efh accesses 70h-7fh f0h accesses 70h-7fh 170h accesses 70h-7fh 1f0h 7fh ffh 17fh 1ffh unimplemented data memory locations, read as ? 0 ? . *not a physical register. note 1: reserved registers may contain usb state information. 2: parallel slave ports (portd and porte) not implemented on pic16c745; always maintain these bits clear. 745cov.book page 16 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 17 pic16c745/765 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the special function registers can be classified into two sets (core and peripheral). those registers associ- ated with the ? core ? functions are described in this sec- tion, and those related to the operation of the peripheral features are described in the section of that peripheral feature. table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) bank 0 00h indf (3) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 02h pcl (3) program counter's (pc) least significant byte 0000 0000 0000 0000 03h status (3) irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 000q quuu 04h fsr (3) indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta ? ? porta data latch when written: porta pins when read --0x 0000 --0u 0000 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc rc7 rc6 ? ? ? rc2 rc1 rc0 xx-- -xxx uu-- -uuu 08h portd (4) portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h porte (4) ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 0ah pclath (1,3) ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh intcon (3) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (4) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 module ? s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h ? unimplemented ? ? 14h ? unimplemented ? ? 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? dc2b1 dc2b1 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ? adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ? 0 ? . shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: the parallel slave port (portd and porte) is not implemented on the pic16c745, always maintain these bits clear. 745cov.book page 17 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 18 preliminary ? 2000 microchip technology inc. bank 1 80h indf (3) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl (3) program counter ? s (pc) least significant byte 0000 0000 0000 0000 83h status (3) irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h fsr (3) indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa ? ? porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc trisc7 trisc8 ? ? ? trisc2 trisc1 trisc0 11-- -111 11-- -111 88h trisd (4) portd data direction register 1111 1111 1111 1111 89h trise (4) ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 8ah pclath (1,3) ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh intcon (3) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (4) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 8eh pcon ? ? ? ? ? ? por bor ---- --qq ---- --uu 8fh ? unimplemented ? ? 90h ? unimplemented ? ? 91h ? unimplemented ? ? 92h pr2 timer2 period register 1111 1111 1111 1111 93h ? unimplemented ? ? 94h ? unimplemented ? ? 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah ? unimplemented ? ? 9bh ? unimplemented ? ? 9ch ? unimplemented ? ? 9dh ? unimplemented ? ? 9eh ? unimplemented ? ? 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 table 4-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ? 0 ? . shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: the parallel slave port (portd and porte) is not implemented on the pic16c745, always maintain these bits clear. 745cov.book page 18 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 19 pic16c745/765 bank 2 100h indf (3) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 101h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 102h pcl (3) program counter's (pc) least significant byte 0000 0000 0000 0000 103h status (3) irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 104h fsr (3) indirect data memory address pointer xxxx xxxx uuuu uuuu 105h ? unimplemented ? ? 106h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah pclath (1,3) ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh intcon (3) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10ch- 11fh ? unimplemented ? ? table 4-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ? 0 ? . shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: the parallel slave port (portd and porte) is not implemented on the pic16c745, always maintain these bits clear. 745cov.book page 19 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 20 preliminary ? 2000 microchip technology inc. bank 3 180h indf (3) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h pcl (3) program counter ? s (pc) least significant byte 0000 0000 0000 0000 183h status (3) irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 184h fsr (3) indirect data memory address pointer xxxx xxxx uuuu uuuu 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 1111 1111 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah pclath (1,3) ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh intcon (3) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 18ch- 18fh ? unimplemented ? ? 190h uir ? ? stall uidle tok_dne activity uerr usb_rst --00 0000 --00 0000 191h uie ? ? stall uidle tok_dne activity uerr usb_rst --00 0000 --00 0000 192h ueir bts_err own_err wrt_err bto_err dfn8 crc16 crc5 pid_err 0000 0000 0000 0000 193h ueie bts_err own_err wrt_err bto_err dfn8 crc16 crc5 pid_err 0000 0000 0000 0000 194h ustat ? ? ? endp1 endp0 in ? ? ---x xx-- ---u uu-- 195h uctrl ? ? seo pkt_dis dev_att resume suspnd ? --x0 000- --xq qqq- 196h uaddr ? addr6 addr5 addr4 addr3 addr2 addr1 addr0 -000 0000 -000 0000 197h uswstat swstat7 swstat6 swstat5 swstat4 swstat3 swstat2 swstat1 swstat0 0000 0000 0000 0000 198h uep0 ? ? ? ? ep_ctl_dis ep_out_en ep_in_en ep_stall ---- 0000 ---- 0000 199h uep1 ? ? ? ? ep_ctl_dis ep_out_en ep_in_en ep_stall ---- 0000 ---- 0000 19ah uep2 ? ? ? ? ep_ctl_dis ep_out_en ep_in_en ep_stall ---- 0000 ---- 0000 19bh- 19fh reserved reserved, do not use. 0000 0000 0000 0000 table 4-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ? 0 ? . shaded locations are unimplemented, read as ? 0 ? . note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank. 4: the parallel slave port (portd and porte) is not implemented on the pic16c745, always maintain these bits clear. 745cov.book page 20 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 21 pic16c745/765 table 4-2: usb dual port ram address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (1) 1a0h bd0ost uown uown data0/1 data0/1 pid3 ? pid2 ? pid1 dts pid0 bstall ? ? ? ? xxxx xxxx uuuu uuuu 1a1h bd0obc ? ? ? ? byte count xxxx xxxx uuuu uuuu 1a2h bd0oal buffer address low xxxx xxxx uuuu uuuu 1a3h ? reserved ? ? 1a4h bd0ist uown uown data0/1 data0/1 pid3 ? pid2 ? pid1 dts pid0 bstall ? ? ? ? xxxx xxxx uuuu uuuu 1a5h bd0ibc ? ? ? ? byte count xxxx xxxx uuuu uuuu 1a6h bd0ial buffer address low xxxx xxxx uuuu uuuu 1a7h ? reserved ? ? 1a8h bd1ost uown uown data0/1 data0/1 pid3 ? pid2 ? pid1 dts pid0 bstall ? ? ? ? xxxx xxxx uuuu uuuu 1a9h bd1obc ? ? ? ? byte count xxxx xxxx uuuu uuuu 1aah bd1oal buffer address low xxxx xxxx uuuu uuuu 1abh ? reserved ? ? 1ach bd1ist uown uown data0/1 data0/1 pid3 ? pid2 ? pid1 dts pid0 bstall ? ? ? ? xxxx xxxx uuuu uuuu 1adh bd1ibc ? ? ? ? byte count xxxx xxxx uuuu uuuu 1aeh bd1ial buffer address low xxxx xxxx uuuu uuuu 1afh ? reserved ? ? 1b0h bd2ost uown uown data0/1 data0/1 pid3 ? pid2 ? pid1 dts pid0 bstall ? ? ? ? xxxx xxxx uuuu uuuu 1b1h bd2obc ? ? ? ? byte count xxxx xxxx uuuu uuuu 1b2h bd2oal buffer address low xxxx xxxx uuuu uuuu 1b3h ? reserved ? ? 1b4h bd2ist uown uown data0/1 data0/1 pid3 ? pid2 ? pid1 dts pid0 bstall ? ? ? ? xxxx xxxx uuuu uuuu 1b5h bd2ibc ? ? ? ? byte count xxxx xxxx uuuu uuuu 1b6h bd2ial buffer address low xxxx xxxx uuuu uuuu 1b7h ? reserved ? ? 1b8h- 1dfh 40 byte usb buffer xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ? 0 ? . shaded locations are unimplemented, read as ? 0 ? . note 1: other (non power-up) resets include external reset through mclr and watchdog timer reset. 745cov.book page 21 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 22 preliminary ? 2000 microchip technology inc. 4.2.2.1 status register the status register, shown in register 4-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended that only bcf, bsf, swapf and movwf instructions be used to alter the status regis- ter. these instructions do not affect the z, c or dc bits in the status register. for other instructions which do not affect status bits, see the "instruction set sum- mary." register 4-1: status register (status: 03h, 83h, 103h, 183h) note 1: the c and dc bits operate as b orrow and digit borrow bits, respectively, in subtrac- tion. see the sublw and subwf instruc- tions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc c (1) r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7: irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp<1:0>: register bank select bits (used for direct addressing) 00 = bank 0 (00h - 7fh) 01 = bank 1 (80h - ffh) 10 = bank 2 (100h - 17fh) 11 = bank 3 (180h - 1ffh) bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc: digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (1) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c: carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow the polarity is reversed. a subtraction is executed by adding the two ? s complement of the sec- ond operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. 745cov.book page 22 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 23 pic16c745/765 4.2.2.2 option register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0/wdt prescaler, the external int interrupt, tmr0 and the weak pull-ups on portb. register 4-2: option register (option_reg: 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps<2:0> : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate 745cov.book page 23 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 24 preliminary ? 2000 microchip technology inc. 4.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 4-3: interrupt control register (intcon: 10bh, 18bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt . r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = at least one of the rb<7:4> pins changed state (must be cleared in software) 0 = none of the rb<7:4> pins have changed state 745cov.book page 24 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 25 pic16c745/765 4.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 4-4: peripheral interrupt enable1 register (pie1: 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5: rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4: txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3: usbie : universal serial bus interrupt enable bit 1 = enables the usb interrupt 0 = disables the usb interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: parallel slave ports not implemented on the pic16c745; always maintain this bit clear. 745cov.book page 25 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 26 preliminary ? 2000 microchip technology inc. 4.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 4-5: peripheral interrupt register1 (pir1: 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6: adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5: rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full (clear by reading rcreg) 0 = the usart receive buffer is empty bit 4: txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (clear by writing to txreg) 0 = the usart transmit buffer is full bit 3: usbif : universal serial bus (usb) interrupt flag 1 = a usb interrupt condition has occurred. the specific cause can be found by examining the contents of the uir and uie registers. 0 = no usb interrupt conditions that are enabled have occurred. bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: parallel slave ports not implemented on the pic16c745; always maintain this bit clear. 745cov.book page 26 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 27 pic16c745/765 4.2.2.6 pie2 register this register contains the individual enable bit for the ccp2 peripheral interrupt. register 4-6: peripheral interrupt enable 2 register (pie2: 8dh) 4.2.2.7 pir2 register this register contains the ccp2 interrupt flag bit. register 4-7: peripheral interrupt register 2 (pir2: 0dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2ie r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2if r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused 745cov.book page 27 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 28 preliminary ? 2000 microchip technology inc. 4.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watchdog reset (wdt) and an external mclr reset. register 4-8: power control register register (pcon: 8eh) note: bor is unknown on por. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q ? ? ? ? ? ? por bor r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bo r : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) 745cov.book page 28 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 29 pic16c745/765 4.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 4-3 shows the two situations for the loading of the pc. the upper example in the fig- ure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the fig- ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 4-3: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note ?implementing a table read" (an556). 4.3.2 stack the pic16c745/765 family has an 8-level deep x 13- bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an inter- rupt causes a branch. the stack is poped in the event of a return,retlw or a retfie instruction execu- tion. pclath is not affected by a push or pop opera- tion. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 4.4 program memory paging pic16cxx devices are capable of addressing a contin- uous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is exe- cuted, the entire 13-bit pc is pushed onto the stack. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). example 4-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt ser- vice routine (if interrupts are used). example 4-1: call of a subroutine in page 1 from page 0 org 0x500 bsf pclath,3 ;select page 1 (800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine : ;page 1 (800h-fffh) : return ;return to call subroutine ;in page 0 (000h-7ffh) pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop . these are actions that occur from the execution of the call, return, retlw, and retfie instruc- tions, or the vectoring to an interrupt address. 745cov.book page 29 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 30 preliminary ? 2000 microchip technology inc. 4.5 i ndirect addressing, indf and fs r r egisters the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself indirectly (fsr = ? 0 ? ) will read 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-4. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 4-2. example 4-2: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue figure 4-4: direct/indirect addressing note: for register file map detail see figure 4-2. data memory indirect addressing direct addressing bank select location select rp<1:0> 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h 745cov.book page 30 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 31 pic16c745/765 5.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. 5.1 porta and trisa registers porta is a 6-bit latch. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. all pins have data direction bits (tris registers), which can config- ure these pins as output or input. setting a trisa register bit puts the corresponding out- put driver in a hi-impedance mode. clearing a bit in the trisa register puts the contents of the output latch on the selected pin(s). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, the value is modified, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. on the pic16c745/765, porta pins are multiplexed with analog inputs and analog v ref input. the opera- tion of each pin is selected by clearing/setting the con- trol bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 5-1: initializing porta (pic16c745/765) bcf status, rp1 ; bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as ?0?. figure 5-1: block diagram of ra<3:0> and ra5 pins figure 5-2: block diagram of ra4/t0cki pin note: on all resets, pins with analog and digi- tal functions are configured as analog inputs. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin analog input mode to a/d converter v dd schmitt trigger input buffer data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin tmr0 clock input q d q ck q d q ck en qd en v dd 745cov.book page 31 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 32 preliminary ? 2000 microchip technology inc. table 5-1: porta functions table 5-2: summary of registers associated with porta name function input type output type description ra0/an0 ra0 st cmos bi-directional i/o an0 an ? a/d input ra1/an1 ra1 st cmos bi-directional i/o an1 an ? a/d input ra2/an2 ra2 st cmos bi-directional i/o an2 an ? a/d input ra3/an3/v ref ra3 st cmos bi-directional i/o an3 an ? a/d input v ref an ? a/d positive reference ra4/t0cki ra4 st od bi-directional i/o t0cki st ? timer 0 clock input ra5/an4 ra5 st bi-directional i/o an4 an ? a/d input legend: od = open drain, st = schmitt trigger address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. 745cov.book page 32 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 33 pic16c745/765 5.2 por tb and trisb registers portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a bit in the trisb register puts the corresponding output driver in a hi-impedance input mode. clearing a bit in the trisb register puts the contents of the output latch on the selected pin(s). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. figure 5-3: block diagram of rb<3:0> pins four of portb ? s pins, rb<7:4>, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb<7:4> pin con- figured as an output is excluded from the interrupt-on- change comparison). the input pins (of rb<7:4>) are compared with the value latched on the last read of portb. the ? mismatch ? outputs of rb<7:4> are or ? ed together to generate the rb port change inter- rupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition, and allow flag bit rbif to be cleared. this interrupt-on-mismatch feature, together with soft- ware configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the embedded control handbook, ? implementing wake-up on key stroke ? (an552). the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. rb0/int is an external interrupt input pin and is config- ured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 13.5.1. figure 5-4: block diagram of rb<7:4> pins data wr wr rb0/int note 1: to enable weak pull-ups, set the appropriate tris bit(s) data latch p v dd q d ck q d ck qd en rd tris rd port weak pull-up rd port i/o pin ttl input buffer schmitt trigger buffer tris latch and clear the rbpu bit (option_reg<7>). v dd bus port tris rbpu (1) data latch from other rbpu (1) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb<7:4> pins weak pull-up rd port latch ttl input buffer pin note 1: to enable weak pull-ups, set the appropriate tris bit(s) st buffer rb<7:6> in serial programming mode q3 q1 and clear the rbpu bit (option_reg<7>). v dd 745cov.book page 33 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 34 preliminary ? 2000 microchip technology inc. table 5-3: portb functions table 5-4: summary of registers associated with portb name function input type output type description rb0/int rb0 ttl cmos bi-directional i/o int st ? interrupt rb1 rb1 ttl cmos bi-directional i/o rb2 rb2 ttl cmos bi-directional i/o rb3 rb3 ttl cmos bi-directional i/o rb4 rb4 ttl cmos bi-directional i/o with interrupt-on-change rb5 rb5 ttl cmos bi-directional i/o with interrupt-on-change rb6/icspc rb6 ttl cmos bi-directional i/o with interrupt-on-change icspc st in-circuit serial programming clock input rb7/icspd rb7 ttl cmos bi-directional i/o with interrupt-on-change icspd st cmos in-circuit serial programming data i/o legend: od = open drain, st = schmitt trigger address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb. 745cov.book page 34 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 35 pic16c745/765 5.3 portc and trisc registers portc is a 5-bit bi-directional port. each pin is individ- ually configureable as an input or output through the trisc register. portc is multiplexed with several peripheral functions (table 5-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. figure 5-5: portc block diagram port/peripheral select (1) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (2) peripheral input i/o pin note 1: port/peripheral select signal selects between port data and peripheral output. 2: peripheral oe (output enable) is only activated if peripheral select is active. v dd 745cov.book page 35 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 36 preliminary ? 2000 microchip technology inc. table 5-5: portc functions table 5-6: summary of registers associated with portc name function input type output type description rc0/t1oso/t1cki rc0 st cmos bi-directional i/o t1oso ? xtal t1 oscillator output t1cki st ? t1 clock input rc1/t1osi/ccp2 rc1 st cmos bi-directional i/o t1osi xtal ? t1 oscillator input ccp2 ?? capture in/compare out/pwm out 2 rc2/ccp1 rc2 st cmos bi-directional i/o ccp1 ?? capture in/compare out/pwm out 1 rc6/tx/ck rc6 st cmos bi-directional i/o tx ? cmos usart async transmit ck st cmos usart master out/slave in clock rc7/rx/dt rc7 st cmos bi-directional i/o rx st ? usart async receive dt st cmos usart data i/o legend: od = open drain, st = schmitt trigger address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 ? ? ? rc2 rc1 rc0 xx-- -xxx uu-- -uuu 87h trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 11-- -111 11-- -111 legend: x = unknown, u = unchanged. 745cov.book page 36 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 37 pic16c745/765 5.4 portd and trisd registers portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configured as an input or output. portd can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 5-6: portd block diagram table 5-7: portd functions table 5-8: summary of registers associated with portd note: the pic16c745 does not provide portd. the portd and trisd registers are reserved. always maintain these bits clear. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin q d ck q d ck en qd en v dd name function input type output type description rd0/psp0 rd0 ttl cmos bi-directional i/o (1) psp0 ttl ? parallel slave port data input (1) rd1/psp1 rd1 ttl cmos bi-directional i/o (1) psp1 ttl ? parallel slave port data input (1) rd2/psp2 rd2 ttl cmos bi-directional i/o (1) psp2 ttl ? parallel slave port data input (1) rd3/psp3 rd3 ttl cmos bi-directional i/o (1) psp3 ttl ? parallel slave port data input (1) rd4/psp4 rd4 ttl cmos bi-directional i/o (1) psp4 ttl ? parallel slave port data input (1) rd5/psp5 rd5 ttl cmos bi-directional i/o (1) psp5 ttl ? parallel slave port data input (1) rd6/psp6 rd6 ttl cmos bi-directional i/o (1) psp6 ttl ? parallel slave port data input (1) rd7/psp7 rd7 ttl cmos bi-directional i/o (1) psp7 ttl ? parallel slave port data input (1) legend: od = open drain, st = schmitt trigger note 1: pic16c765 only. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd (1) rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd (1) portd data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portd. note 1: pic16c765 only. 745cov.book page 37 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 38 preliminary ? 2000 microchip technology inc. 5.5 porte and trise register s porte has three pins, re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually configured as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs) and that register adcon1 is configured for dig- ital i/o. in this mode, the input buffers are ttl. register 5-1 shows the trise register, which also con- trols the parallel slave port operation. porte pins may be multiplexed with analog inputs (pic16c765 only). the operation of these pins is selected by control bits in the adcon1 register. when selected as an analog input, these pins will read as ? 0 ? s. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. trise bits are used to control the parallel slave port. figure 5-7: porte block diagram table 5-9: porte (1) functions note 1: the pic16c745 does not provide porte. the porte and trise registers are reserved. always maintain these bits clear. note: on a power-on reset, these pins are con- figured as analog inputs. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer q d ck q d ck en qd en i/o pin to a/d converter v dd name function input type output type description re0/rd /an5 re0 st cmos bi-directional i/o (1) rd ttl ? parallel slave port control input (1) an5 an ? a/d input (1) re1/wr /an6 re1 st cmos bi-directional i/o (1) wr ttl ? parallel slave port control input (1) an6 an ? a/d input (1) re2/cs /an7 re2 st cmos bi-directional i/o (1) cs ttl ? parallel slave port data input (1) an7 an ? a/d input (1) legend: od = open drain, st = schmitt trigger note 1: pic16c765 only. 745cov.book page 38 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 39 pic16c745/765 register 5-1: porte data direction control register (1) (trise: 89h) table 5-10: summary of registers associated with porte r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? trise2 trise1 trise0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7 : ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6: obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5: ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4: pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3: unimplemented : read as '0' porte data direction bits bit 2: trise2 : direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1: trise1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0: trise0 : direction control bit for pin re0/rd /an5 1 = input 0 = output note 1: pic16c765 only. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte (1) ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise (1) ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte. note 1: pic16c765 only. 745cov.book page 39 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 40 preliminary ? 2000 microchip technology inc. 5.6 parallel slave port (psp) portd operates as an 8-bit wide parallel slave port (psp), or microprocessor port when control bit psp- mode (trise<4>) is set. in slave mode, it is asyn- chronously readable and writable by the external world through rd control input pin re0/rd /an5 and wr control input pin re1/wr /an6. it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd /an5 to be the rd input, re1/ wr /an6 to be the wr input and re2/cs /an7 to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set) and the a/d port configuration bits pcfg<2:0> (adcon1<2:0>) must be set, which will configure pins re<2:0> as digital i/o. there are actually two 8-bit latches; one for data-out (from the picmicro ? microcontroller) and one for data input. the user writes 8-bit data to portd data latch and reads data from the port pin latch (note that they have the same address). in this mode, the trisd reg- ister is ignored, since the microprocessor is controlling the direction of data flow. a write to the psp occurs when both the cs and wr lines are first detected low. when either the cs or wr lines become high (level triggered), then the input buffer full (ibf) status flag bit (trise<7>) is set on the q4 clock cycle, following the next q2 cycle, to signal the write is complete (figure 5-9). the interrupt flag bit pspif (pir1<7>) is also set on the same q4 clock cycle. ibf can only be cleared by reading the portd input latch. the input buffer overflow (ibov) status flag bit (trise<5>) is set if a second write to the psp is attempted when the previous byte has not been read out of the buffer. a read from the psp occurs when both the cs and rd lines are first detected low. the output buffer full (obf) status flag bit (trise<6>) is cleared immedi- ately (figure 5-10) indicating that the portd latch is waiting to be read by the external bus. when either the cs or rd pin becomes high (level triggered), the inter- rupt flag bit pspif is set on the q4 clock cycle, follow- ing the next q2 cycle, indicating that the read is complete. obf remains low until data is written to portd by the user firmware. when not in psp mode, the ibf and obf bits are held clear. however, if flag bit ibov was previously set, it must be cleared in firmware. an interrupt is generated and latched into flag bit pspif when a read or write operation is completed. pspif must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). figure 5-8: portd and porte block diagram (parallel slave port) note: the pic16c745 does not provide a paral- lel slave port. the portd, porte, trisd and trise registers are reserved. always maintain these bits clear. data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr ttl ttl ttl ttl v dd 745cov.book page 40 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 41 pic16c745/765 figure 5-9: parallel slave port write waveforms figure 5-10: parallel slave port read waveforms table 5-11: registers associated with parallel slave port address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd (2) port data latch when written: port pins when read xxxx xxxx uuuu uuuu 09h porte (2) ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise (2) ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the parallel slave port. note 1: bits pspie and pspif are reserved on the pic16c745. always maintain these bits clear. 2: pic16c765 only. q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> 745cov.book page 41 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 42 preliminary ? 2000 microchip technology inc. notes: 745cov.book page 42 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 43 pic16c745/765 6.0 timer0 module the timer0 module timer/counter has the following fea- tures: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt-on-overflow from ffh to 00h edge select for external clock figure 6-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. additional information on the timer0 module is avail- able in the picmicro ? mid-range mcu family refer- ence manual (ds33023). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in detail in section 6.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler is not readable or writable. section 6.3 details the operation of the prescaler. 6.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut off during sleep. figure 6-1: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x f int sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa tocs prescaler 745cov.book page 43 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 44 preliminary ? 2000 microchip technology inc. 6.2 u sing timer0 with an external cloc k when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 6.3 p re scaler there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watch- dog timer, and vice-versa. this prescaler is not readable or writable (see figure 6-1). the psa and ps<2:0> bits (option_reg<3:0>) deter- mine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. to avoid an unintended device reset, the following instruction sequence (shown in example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be fol- lowed even if the wdt is disabled. example 6-1: changing prescaler (timer0 wdt) table 6-1: registers associated with timer0 note: writing to tmr0, when the prescaler is assigned to timer0, will clear the prescaler count, but will not change the prescaler assignment. 1) bsf status, rp0 ;bank1 lines 2 and 3 do not have to be included if the final desired prescale value is other than 1:1. if 1:1 is the final desired value, then a temporary prescale value is set in lines 2 and 3 and the final prescale value will be set in lines 10 and 11. 2) movlw b?xx0x0xxx? ;select clock source and prescale value of 3) movwf option_reg ;other than 1:1 4) bcf status, rp0 ;bank0 5) clrf tmr0 ;clear tmr0 and prescaler 6) bsf status, rp1 ;bank1 7) movlw b?xxxx1xxx? ;select wdt, do not change prescale value 8) movwf option_reg ; 9) clrwdt ;clears wdt and prescaler 10) movlw b?xxxx1xxx? ;select new prescale value and wdt 11) movwf option_reg ; 12) bcf status, rp0 ;bank0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. 745cov.book page 44 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 45 pic16c745/765 7.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: as a timer as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). timer1 also has an internal ? reset input ? . this reset can be generated by either of the two ccp modules (section 9.0). register 7-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). register 7-1: timer1 control register (t1con: 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps<1:0> : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off (the oscillator inverter is turned off to eliminate power drain) bit 2: t1sync : timer1 external clock input synchronization control bit t mr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input t mr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (1) or rc1/t1osi/ccp2 0 = internal clock (f int ) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1 note 1: on the rising edge after the first falling edge. 745cov.book page 45 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 46 preliminary ? 2000 microchip technology inc. 7.1 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f int . the synchronize control bit t1sync (t1con<2>) has no effect since the internal clock is always in sync. 7.2 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2, when bit t1oscen is set, or on pin rc0/t1oso/t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the pres- caler stage is an asynchronous ripple-counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. the pres- caler however will continue to increment. figure 7-1: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps<1:0> sleep input t1oscen enable oscillator (1) f int internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi/ccp2 note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1 745cov.book page 46 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 47 pic16c745/765 7.3 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt-on-overflow, which will wake-up the processor. however, special precautions in soft- ware are needed to read/write the timer (section 7.3.1). in asynchronous counter mode, timer1 can not be used as a time-base for capture or compare operations. 7.3.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will guarantee a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. examples 12-2 and 12-3 in the picmicro ? mid-range mcu fam- ily reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 7.4 t imer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for use with a 32 khz crystal. table 7-1 shows the capacitor selection for the timer1 oscillator. table 7-1: capacitor selection for the timer1 oscillator 7.5 resetting timer1 using a ccp trigger output if the ccp1 or ccp2 module is configured in compare mode to generate a ? special event trigger ? (ccp1m<3:0> = 1011 ), this signal will reset timer1. timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1 or ccp2, the write will take precedence. in this mode of operation, the ccprxh:ccprxl regis- ter pair effectively becomes the period register for timer1. 7.6 resetting of timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por or any other reset except by the ccp1 and ccp2 special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 7.7 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. note: the special event triggers from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>). 745cov.book page 47 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 48 preliminary ? 2000 microchip technology inc. table 7-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. 745cov.book page 48 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 49 pic16c745/765 8.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time-base for the pwm mode of the ccp module(s). the tmr2 reg- ister is readable and writable, and is cleared on any device reset. the input clock (f int /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps<1:0> (t2con<1:0>). the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. register 8-1 shows the timer2 control register. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). 8.1 t imer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (por, mclr reset, wdt reset or bor) tmr2 is not cleared when t2con is written. figure 8-1: timer2 block diagram register 8-1: timer2 control register (t2con: 12h) comparator tmr2 sets flag tmr2 reg output reset postscaler prescaler pr2 reg 2 f int 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if to t2outps<3:0> t2ckps<1:0> u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w= writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps<3:0> : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps<1:0> : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 745cov.book page 49 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 50 preliminary ? 2000 microchip technology inc. table 8-1: registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif ( 1 ) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie ( 1 ) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module ? s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. 745cov.book page 50 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 51 pic16c745/765 9.0 capture/compare/pwm modules each capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: 16-bit capture register 16-bit compare register pwm master/slave duty cycle register both the ccp1 and ccp2 modules are identical in operation, with the exception being the operation of the special event trigger. table 9-1 and table 9-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 operates the same as ccp1, except where noted. ccp1 m odule: capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match and will reset timer1. ccp2 module: capture/compare/pwm register1 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. the special event trigger is generated by a compare match and will reset timer1 and start an a/d conversion (if the a/d module is enabled). additional information on ccp modules is available in the picmicro ? mid-range mcu family reference manual (ds33023) and in ? using the ccp modules ? (an594). table 9-1: ccp mode - timer resources required table 9-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be configured for the special event trigger, which clears tmr1. compare compare the compare(s) should be configured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none. 745cov.book page 51 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 52 preliminary ? 2000 microchip technology inc. register 9-1: capture/compare/pwm control register (ccp1con: 17h, ccp2con: 1dh) u u r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcnb1 dcnb0 ccpnm3 ccpnm2 ccpnm1 ccpnm0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: dcnb<1:0>: pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprnl. bit 3-0: ccpnm<3:0>: ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpn module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpnif bit is set) 1001 = compare mode, clear output on match (ccpnif bit is set) 1010 = compare mode, generate software interrupt on match (ccpnif bit is set, ccpn pin is unaffected) 1011 = compare mode, trigger special event (ccpnif bit is set; ccpn resets tmr1or tmr3) 11xx = pwm mode 745cov.book page 52 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 53 pic16c745/765 9.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m<3:0> (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 9.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. figure 9-1: capture mode operation block diagram 9.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 9.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 9.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m<3:0>. whenever the ccp module is turned off, or the ccp module is not in capture mode, the pres- caler counter is cleared. any reset will clear the pres- caler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 9-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ? false ? interrupt. example 9-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new precscaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a cap- ture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable q ? s ccp1con<3:0> rc2/ccp1 prescaler 1, 4, 16 and edge detect pin 745cov.book page 53 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 54 preliminary ? 2000 microchip technology inc. 9.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccp1m<3:0> (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 9-2: compare mode operation block diagram 9.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 9.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 9.2.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccpif bit is set causing a ccp interrupt (if enabled). 9.2.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp2 starts an a/d conversion (if the a/d module is on) and resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). 9.3 pwm mode (pwm) in pulse width modulation mode, the ccpx pin pro- duces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 9-3 shows a simplified block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 9.3.3. figure 9-3: simplified pwm block diagram a pwm output (figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). the fre- quency of the pwm is the inverse of the period (1/period). note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>). note: the special event trigger from the ccp1and ccp2 modules will not set inter- rupt flag bit tmr1if (pir1<0>). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc <2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time base. 745cov.book page 54 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 55 pic16c745/765 figure 9-4: pwm output 9.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 9.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) tosc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: 9.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. note: the timer2 postscaler (see section 8.1) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. period duty cycle (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. ccp1 (2) 2: output signal is shown as asserted high. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f int ) bits = resolution 745cov.book page 55 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 56 preliminary ? 2000 microchip technology inc. table 9-3: registers associated with capture, compare, and timer1 table 9-4: registers associated with pwm and timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? dcnb1 dcnb0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? dcnb1 dcnb0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as ? 0 ? . shaded cells are not used by capture and timer1. note 1: the psp is not implemented on the pic16c745; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module ? s register 0000 0000 0000 0000 92h pr2 timer2 module ? s period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? dcnb1 dcnb0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? dcnb1 dcnb0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. 745cov.book page 56 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 57 pic16c745/765 10.0 universal serial bus 10.1 overview this section introduces a minimum amount of informa- tion on usb. if you already have basic knowledge of usb, you can safely skip this section. if terms like enumeration, endpoint, in/out transactions, trans- fers and low speed/full speed are foreign to you, read on. usb was developed to address the increased connec- tivity needs of pc ? s in the pc 2000 specification. there was a base requirement to increase the band- width and number of devices, which could be attached. also desired were the ability for hot swap- ping, user friendly operation, robust communications and low cost. the primary promoters of usb are intel, compaq, microsoft and nec. usb is implemented as a tiered star topology, with the host at the top, hubs in the middle, spreading out to the individual devices at the end. usb is limited to 127 devices on the bus, and the tree cannot be more than 6 levels deep. usb is a host centric architecture. the host is always the master. devices are not allowed to ? speak ? unless ? spoken to ? by the host. transfers take place at one of two speeds. full speed is 12 mb/s and low speed is 1.5 mb/s. full speed covers the middle ground of data intensive audio and compressed video applications, while low speed sup- ports less data intensive applications. 10.1.1 transfer protocols full speed supports four transfer types: isochronous, bulk, interrupt and control. low speed supports two transfer types: interrupt and control. the four transfer types are described below. - isochronous transfers , meaning equal time, guarantee a fixed amount of data at a fixed rate. this mode trades off guaranteed data accuracy for guaranteed timeliness. data validity is not checked because there isn ? t time to re-send bad packets anyway and the consequences of bad data are not catastrophic. - bulk transfers are the converse of iso- chronous. data accuracy is guaranteed, but timeliness is not. - interrupt transfers are designed to commu- nicate with devices which have a moderate data rate requirement. human interface devices like keyboards are but one example. for interrupt transfers, the key is the desire to transfer data at regular intervals. usb peri- odically polls these devices at a fixed rate to see if there is data to transfer. - control transfers are used for configuration purposes. 10.1.2 frames information communicated on the bus is grouped in a format called frames. each frame is 1 ms in duration and is composed of multiple transfers. each transfer type can be repeated more than once within a frame. 10.1.3 power power has always been a concern with any device. with usb, 5 volt power is now available directly from the bus. devices may be self-powered or bus- powered. self-powered devices will draw power from a wall adapter or power brick. on the other hand, bus- powered devices will draw power directly from the usb bus itself. there are limits to how much power can be drawn from the usb bus. power is expressed in terms of ? unit loads ? ( 100 ma). all devices, includ- ing hubs, are guaranteed at least 1 unit load (low power), but must negotiate with the host for up to 5 unit loads (high power). if the host determines that the bus as currently configured cannot support a device ? s request for more unit loads, the device will be denied the extra unit loads and must remain in a low power configuration. 10.1.4 end points at the lowest level, each device controls one or more endpoints. an endpoint can be thought of as a virtual port. endpoints are used to communicate with a device ? s functions. each endpoint is a source or sink of data. endpoints have both an in and out direction associated with it. each device must implement end- point 0 to support control transfers for configuration. there are a maximum of 15 endpoints available for use by each full speed device and 6 endpoints for each slow speed device. remember that the bus is host centric, so in/out is with respect to the host and not the device. 10.1.5 enumeration prior to communicating on the bus, the host must see that a new device has been connected and then go through an ? enumeration process ? . this process allows the host to ask the device to introduce itself, and negotiate performance parameters, such as power consumption, transfer protocol and polling rate. the enumeration process is initiated by the host when it detects that a new device has attached itself to the bus. this takes place completely in the background from the application process. 10.1.6 descriptors the usb specification requires a number of different descriptors to provide information necessary to identify a device, specify its endpoints, and each endpoint ? s function. the five general categories of descriptors are device, configuration, interface, end point and string. 745cov.book page 57 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 58 preliminary ? 2000 microchip technology inc. the device descriptor provides general information such as manufacturer, product number, serial number, usb device class the product falls under, and the number of different configurations supported. there can only be one device descriptor for any given appli- cation. the configuration descriptor provides information on the power requirements of the device and how many different interfaces are supported when in this configu- ration. there may be more than one configuration for each device, (i.e., a high power device may also sup- port a low power configuration). the interface descriptor details the number of end- points used in this interface, as well as the class driver to use should the device support functions in more than just one device class. there can only be one interface descriptor for each configuration. the endpoint descriptor details the actual registers for a given function. information is stored about the trans- fer types supported, direction (in/out), bandwidth requirements and polling interval. there may be more than one endpoint in a device, and endpoints may be shared between different interfaces. many of the four descriptors listed above will reference or index different string descriptors. string descriptors are used to provide vendor specific or application spe- cific information. they may be optional and are encoded in ? unicode ? format. 10.1.7 device classes/class drivers operating systems provide drivers which group func- tions together by common device types called classes. examples of device classes include, but are not limited to, storage, audio, communications and hid (human interface). class drivers for a given application are ref- erenced in both the device descriptor and interface descriptor. most applications can find a class driver which supports the majority of their function/command needs. vendors who have a requirement for specific commands which are not supported by any of the standard class drivers may provide a vendor specific ? .inf ? file or driver for extra support. 10.1.8 summary while a complete usb overview is beyond the scope of this document, a few key concepts must be noted. low speed communication is designed for devices, which in the past, used an interrupt to communicate with the host. in the usb scheme, devices do not directly interrupt the processor when they have data. instead the host periodically polls each device to see if they have any data. this polling rate is negotiated between the device and host, giving the system a guaranteed latency. for more details on usb, see the usb v1.1 spec, available from the usb website at www.usb.org. 10.2 i ntroduction the pic16c745/765 usb peripheral module supports low speed control and interrupt (in and out) trans- fers only. the implementation supports 3 endpoint numbers (0, 1, 2) for a total of 6 endpoints. the following terms are used in the description of the usb module: mcu - the core processor and corresponding firmware sie - serial interface engine: that part of the usb that performs functions such as crc gener- ation and clocking of the d+ and d- signals. usb - the usb module including sie and registers bit stuffing - forces insertion of a transition on d+ and d- to maintain clock synchronization bd - buffer descriptor bdt - buffer descriptor table ep - endpoint (combination of endpoint number and direction) in - packet transfer into the host out - packet transfer out of the host 10.3 usb transaction when the usb transmits or receives data the sie will first check that the corresponding endpoint and direc- tion buffer description uown bit equals 1. the usb will move the data to or from the corresponding buffer. when the token is complete, the usb will update the bd status and change the uown bit to 0. the ustat register is updated and the tok_dne interrupt is set. when the mcu processes the tok_dne interrupt it reads the ustat register, which gives the mcu the information it needs to process the endpoint. at this point the mcu will process the data and set the corre- sponding uown bit. figure 10-1 shows a time line of how a typical usb token would be processed. 10.4 firmware support microchip provides a comprehensive support library of standard chapter 9 usb commands. these libraries provide a software layer to insulate the application software from having to handle the complexities of the usb protocol. a simple put/get interface is imple- mented to allow most of the usb processing to take place in the background within the usb interrupt ser- vice routine. applications are encouraged to use the provided libraries during both enumeration and config- ured operation. 745cov.book page 58 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 59 pic16c745/765 figure 10-1: usb tokens usb reset ack setup token data usb_rst interrupt generated tok_dne interrupt generated ack in token data tok_dne interrupt generated ack out token data tok_dne interrupt generated = host = device 745cov.book page 59 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 60 preliminary ? 2000 microchip technology inc. 10.5 usb register map the usb control registers, buffer descriptors and buffers are located in bank 3. 10.5.1 control and status registers the usb module is controlled by 7 registers, plus those that control each endpoint and endpoint/ direction buffer. 10.5.1.1 usb interrupt register (uir) the usb interrupt status register (uir) contains flag bits for each of the interrupt sources within the usb. each of these bits are qualified with their respective interrupt enable bits (see the interrupt enable register uie). all bits of the register are logically or ? ed together to form a single interrupt source for the micro- processor interrupt found in pir1 (usbif). once an interrupt bit has been set, it must be cleared by writing a zero. register 10-1: usb interrupt flags register (uir: 190h) u-0 u-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 ? ? stall uidle tok_dne activity uerr usb_rst r = readable bit c = clearable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5: stall: a stall handshake was sent by the sie bit 4: uidle: this bit is set if the usb has detected a constant idle on the usb bus signals for 3 ms. the idle timer is reset by activity on the usb bus. once a idle condition has been detected, the user may wish to place the usb module in suspend by setting the suspend bit in the uctrl register. bit 3: tok_dne: this bit is set when the current token being processed is complete. the microprocessor should immediately read the ustat register to determine the endpoint number and direction used for this token. clearing this bit causes the ustat register to be cleared or the ustat holding register to be loaded into the stat register if another token has been processed. bit 2: activity: activity on the d+/d- lines will cause the sie to set this bit. typically this bit is unmasked following detection of sleep. users must enable the activity interrupt in the usb interrupt register (uie: 191h) prior to entering suspend. bit 1: uerr: this bit is set when any of the error conditions within the err_stat register has occurred. the mcu must then read the err_stat register to determine the source of the error. bit 0: usb_rst: this bit is set when the usb has decoded a valid usb reset. this will inform the mcu to write 00h into the address register and enable endpoint 0. usb_rst is set once a usb reset has been detected for 2.5 microseconds. it will not be asserted again until the usb reset condition has been removed, and then reasserted. note 1: bits can only be modified when uctrl.suspnd = 0. 745cov.book page 60 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 61 pic16c745/765 10.5.1.2 usb interrupt enable register (uie) the usb interrupt enable register (uie) contains enable bits for each of the interrupt sources within the usb. setting any of these bits will enable the respec- tive interrupt source in the uir register. the values in the uie register only affect the propagation of an inter- rupt condition to the pie1 register. interrupt conditions can still be polled and serviced. register 10-2: usb interrupt enable register (uie: 191h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? stall uidle tok_dne activity uerr usb_rst r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5: stall: set to enable stall interrupts 1 = stall interrupt enabled 0 = stall interrupt disabled bit 4: uidle: set to enable idle interrupts 1 = idle interrupt enabled 0 = idle interrupt disabled bit 3: tok_dne: set to enable tok_dne interrupts 1 = tok_dne interrupt enabled 0 = tok_dne interrupt disabled bit 2 (1) : activity: set to enable activity interrupts 1 = activity interrupt enabled 0 = activity interrupt disabled bit 1: uerr: set to enable error interrupts 1 = error interrupt enabled 0 = error interrupt disabled bit 0: usb_rst: set to enable usb_rst interrupts 1 = usb_rst interrupt enabled 0 = usb_rst interrupt disabled note 1: this interrupt is the only interrupt active during uctrl.suspend = 1. 745cov.book page 61 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 62 preliminary ? 2000 microchip technology inc. 10.5.1.3 usb error interrupt status register (ueir) the usb error interrupt status register (ueir) con- tains bits for each of the error sources within the usb. each of these bits are enabled by their respective error enable bits (ueie). the result is or ? ed together and sent to the error bit of the uir register. once an interrupt bit has been set it must be cleared by writ- ing a zero to the respective interrupt bit. each bit is set as soon as the error condition is detected. thus, the interrupt will typically not correspond with the end of a token being processed. register 10-3: usb error interrupt flags status register (ueir: 192h) r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 bts_err own_err wrt_err bto_err dfn8 crc16 crc5 pid_err r = readable bit c = clearable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: bts_err: a bit stuff error has been detected bit 6: own_err: this bit is set if the usb is processing a token and the own bit within the bdt is equal to 0 (signifying that the microprocessor owns the bdt and the sie does not have access to the bdt). if process- ing an in token this would cause a transmit data underflow condition. processing an out or setup token would cause a receive data overflow condition. bit 5: wrt_err: write error a write by the mcu to the usb buffer descriptor table or buffer area was unsuccessful. this error occurs when the mcu attempts to write to the same location that is currently being written to by the sie. bit 4: bto_err: this bit is set if a bus turnaround time-out error has occurred. this usb uses a bus turnaround timer to keep track of the amount of time elapsed between the token and data phases of a setup or out token or the data and handshake phases of a in token. if more than 17-bit times are counted from the previous eop before a transition from idle, a bus turnaround time-out error will occur. bit 3: dfn8: the data field received was not 8 bits. the usb specification 1.1 specifies that data field must be an integral number of bytes. if the data field was not an integral number of bytes this bit will be set. bit 2: crc16: the crc16 failed bit 1: crc5: this interrupt will detect crc5 error in the token packets generated by the host. if set the token packet was rejected due to a crc5 error. bit 0: pid_err: the pid check field failed note 1: bits can only be modified when uctrl.suspnd = 0. 745cov.book page 62 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 63 pic16c745/765 10.5.1.4 error interrupt enable register (ueie) the usb error interrupt enable register (ueie) con- tains enable bits for each of the error interrupt sources within the usb. setting any of these bits will enable the respective error interrupt source in the ueir regis- ter. register 10-4: usb error interrupt enable register (ueie: 193h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bts_err own_err wrt_err bto_err dfn8 crc16 crc5 pid_err r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: bts_err: set this bit to enable bts_err interrupts 1 = bts_err interrupt enabled 0 = bts_err interrupt disabled bit 6: own_err: set this bit to enable own_err interrupts 1 = own_err interrupt enabled 0 = own_err interrupt disabled bit 5: wrt_err: set this bit to enable wrt_err interrupts 1 = wrt_err interrupt enabled 0 = wrt_err interrupt disabled bit 4: bto_err: set this bit to enable bto_err interrupts 1 = bto_err interrupt enabled 0 = bto_err interrupt disabled bit 3: dfn8: set this bit to enable dfn8 interrupts 1 = dfn8 interrupt enabled 0 = dfn8 interrupt disabled bit 2: crc16: set this bit to enable crc16 interrupts 1 = crc16 interrupt enabled 0 = crc16 interrupt disabled bit 1: crc5: set this bit to enable crc5 interrupts 1 = crc5 interrupt enabled 0 = crc5 interrupt disabled bit 0: pid_err: set this bit to enable pid_err interrupts 1 = pid_err interrupt enabled 0 = pid_err interrupt disabled 745cov.book page 63 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 64 preliminary ? 2000 microchip technology inc. 10.5.1.5 status register (ustat) the usb status register reports the transaction sta- tus within the usb. when the mcu recognizes a tok_dne interrupt, this register should be read to determine the status of the previous endpoint commu- nication. the data in the status register is valid when the tok_dne interrupt bit is asserted. the ustat register is actually a read window into a status fifo maintained by the usb. when the usb uses a bd, it updates the status register. if another usb transaction is performed before the tok_dne interrupt is serviced the usb will store the status of the next transaction in the stat fifo. thus, the stat register is actually a four byte fifo which allows the mcu to process one transaction while the sie is pro- cessing the next. clearing the tok_dne bit in the int_stat register causes the sie to update the stat register with the contents of the next stat value. if the data in the stat holding register is valid, the sie will immediately reassert the tok_dne interrupt. register 10-5: usb status register (ustat: 194h) u-0 u-0 u-0 r-x r-x r-x u-0 u-0 ? ? ? endp1 endp0 in ? ? r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset x = don ? t care bit7 bit0 bit 7-5: unimplemented: read as ? 0 ? bit 4-3: endp<1:0>: these bits encode the endpoint address that received or transmitted the previous token. this allows the microprocessor to determine which bdt entry was updated by the last usb transaction. bit 2: in: this bit indicates the direction of the last bd that was updated 1 = the last transaction was an in token 0 = the last transaction was an out or setup token bit 1-0: unimplemented: read as ? 0 ? 745cov.book page 64 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 65 pic16c745/765 10.5.1.6 usb control register (uctrl) the control register provides various control and con- figuration information for the usb. register 10-6: usb control register (uctrl: 195h) u-0 u-0 r-x r/c-0 r/w-0 r/w-0 r/w-0 u-0 ? ? se0 pkt_dis dev_att resume suspnd ? r = readable bit w = writable bit c = clearable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset x = don ? t care bit7 bit0 bit 7-6: unimplemented: read as ? 0 ? bit 5: se0: live single ended zero this status bit indicates that the d+ and d- lines are both pulled to low. 1 = single ended zero being received 0 = single ended zero not being received bit 4 pkt_dis: the pkt_dis bit informs the mcu that the sie has disabled packet transmission and recep- tion. clearing this bit allows the sie to continue token processing. this bit is set by the sie when a setup token is received allowing software to dequeue any pending packet transactions in the bdt before resum- ing token processing. the pkt_dis bit is set under certain conditions such as back to back setup tokens. this bit is not set on every setup token and can be modified only when uctrl.suspnd = 0. bit 3: dev_att: device attach enables the 3.3v output. 1 = when dev_att is set, the v usb pin will be driven with 3.3v (nominal) 0 = the v usb pins (d+ and d-) will be in a high impedance state bit 2: resume: setting this bit will allow the usb to execute resume signaling. this will allow the usb to perform remote wake-up. software must set resume to 1 for 10 ms then clear it to 0 to enable remote wake-up. for more information on resume signaling, see section 7.1.7.5, 11.9 and 11.4.4 in the usb 1.1 specification. 1 = perform resume signaling 0 = normal operation bit 1: suspnd: suspends usb operation and clocks and places the module in low power mode. this bit will generally be set in response to a uidle interrupt. it will generally be reset after an activity interrupt. v usb regulation will be different between suspend and non-suspend modes. the v usb pin will still be driven, however the transceiver outputs are disabled. 1 = usb module in power conserve mode 0 = usb module normal operation bit 0: unimplemented: read as ? 0 ? 745cov.book page 65 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 66 preliminary ? 2000 microchip technology inc. 10.5.1.7 usb address register (uaddr) the address register (uaddr) contains the unique usb address that the usb will decode. the register is reset to 00h after the reset input has gone active or the usb has decoded a usb reset signaling. that will initialize the address register to decode address 00h as required by the usb specification. the usb address must be written by the mcu during the usb setup phase. register 10-7: usb address register (uaddr: 196h) 10.5.1.8 usb software status register (uswstat) this register is used by the usb firmware libraries for usb status. register 10-8: reserved software library register (uswstat: 197h):. u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? addr6 addr5 addr4 addr3 addr2 addr1 addr0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7: unimplemented: read as ? 0 ? bit 6-0: addr<6:0>: this 7-bit value defines the usb address that the usb will decode warning: writing to this register may cause the sie to drop off the bus. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset 7 6 5 4 3 21 0 reserved for ch9 firmware enumeration status bit 7-2 (1) : reserved: read as ? x ? bit 1-0: w enumeration status <1:0>: status of usb peripheral during enumeration 00 = powered 01 = default 10 = addressed 11 = configured note 1: application should not modify these bits. 745cov.book page 66 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 67 pic16c745/765 10.5.1.9 endpoint registers each endpoint is controlled by an endpoint control register. the pic16c745/765 supports buffer descriptors (bd) for the following endpoints: - ep0 out - ep0 in - ep1 out - ep1 in - ep2 out - ep2 in the user will be required to disable unused endpoints and directions using the endpoint control registers. 10.5.1.10 usb endpoint control register (epcn) the endpoint control register contains the endpoint control bits for each of the 6 endpoints available on usb for a decoded address. these four bits define the control necessary for any one endpoint. endpoint 0 (endp0) is associated with control pipe 0 which is required by usb for all functions (in, out, and setup). therefore, after a usb_rst interrupt has been received, the microprocessor should set uep0 to contain 06h. register 10-9: usb endpoint control register (uepn: 198h-19ah) note: these registers are initialized in response to a reset from the host. the user must modify function usbreset in usb_ch9.asm to configure the endpoints as needed for the application. u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ep_ctl_dis ep_out_en ep_in_en ep_stall r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset bit7 bit0 bit 7-4: unimplemented: read as ? 0 ? bit 3-1: ep_ctl_dis, ep_out_en, ep_in_en: these three bits define if an endpoint is enabled and the direc- tion of the endpoint. the endpoint enable/direction control is defined as follows: bit 0: ep_stall: when this bit is set it indicates that the endpoint is stalled. this bit has priority over all other control bits in the endpoint enable register, but is only valid if ep_in_en=1 or ep_out_en=1. any access to this endpoint will cause the usb to return a stall handshake. the ep_stall bit can be set or cleared by the sie. refer to the usb 1.1 specification, sections 4.4.4 and 8.5.2 for more details on the stall protocol. ep_ctl_dis ep_out_en ep_in_en endpoint enable/direction control x 0 0 disable endpoint x 0 1 enable endpoint for in tokens only x 1 0 enable endpoint for out tokens only 1 1 1 enable endpoint for in and out tokens 0 1 1 enable endpoint for in, out, and setup tokens 745cov.book page 67 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 68 preliminary ? 2000 microchip technology inc. 10.6 buffer descriptor table (bdt) to efficiently manage usb endpoint communications the usb implements a buffer descriptor table (bdt) in register space. every endpoint requires a 4 byte buffer descriptor (bd) entry. because the buffers are shared between the mcu and the usb, a simple semaphore mechanism is used to distinguish which is allowed to update the bd and buffers in system mem- ory. the uown bit is cleared when the bd entry is ? owned ? by the mcu. when the uown bit is set to 1, the bd entry and the buffer in system memory is owned by the usb. the mcu should not modify the bd or its corresponding data buffer. the buffer descriptors provide endpoint buffer control information for the usb and mcu. the buffer descrip- tors have different meaning based on the value of the uown bit. the usb controller uses the data stored in the bds when uown = 1 to determine: data0 or data1 pid data toggle synchronization enable number of bytes to be transmitted or received starting location of the buffer the mcu uses the data stored in the bds when uown = 0 to determine: data0 or data1 pid the received token pid number of bytes transmitted or received each endpoint has a 4 byte buffer descriptor and points to a data buffer in the usb dual port register space. control of the bd and buffer would typically be handled in the following fashion: the mcu verifies uown = 0, sets the bdndal to point to the start of a buffer, if necessary fills the buffer, then sets the bdndst byte to the desired value with uown = 1. when the host commands an in or out transac- tion, the serial interface engine (sie) performs the following: - get the buffer address - read or write the buffer - update the ustat register - update the buffer descriptors with the packet id (pid) value - set the data 0/1 bit - update the byte count - clear the uown bit the mcu is interrupted and reads the ustat, translates that value to a bd, where the uown, pid, data 0/1, and byte count values are checked. warning: the bit entries should be written as a whole word instead of using bsf, bcf to affect individual bits. this is because of the dual meaning of the bits. bit sets and clears may leave other bits set incor- rectly and present incorrect data to the sie. 745cov.book page 68 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 69 pic16c745/765 register 10-10: buffer descriptor status register. bits written by the mcu (bdndst: 1a0h, 1a4h, 1a8h, 1ach, 1b0h, 1b4h) w-x w-x u-x u-x w-x w-x u-x u-x uown data0/1 ? ? dts bstall ? ? r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset x = don ? t care bit7 bit0 bit 7: uown: usb own this uown bit determines who currently owns the buffer. the sie writes a 0 to this bit when it has com- pleted a token. this byte of the bd should always be the last byte the mcu updates when it initializes a bd. once the bd has been assigned to the usb, the mcu should not change it in any way. 1 = usb has exclusive access to the bd. the mcu should not modify the bd or buffer. 0 = the mcu has exclusive access to the bd. the usb ignores all other fields in the bd. bit 6: data0/1: this bit defines the type of data toggle packet that was transmitted or received 1 = data 1 packet 0 = data 0 packet bit 5-4: reserved: read as ? x ? bit 3: dts: setting this bit will enable the usb to perform data toggle synchronization. if a packet arrives with an incorrect dts, it will be ignored and the buffer will remain unchanged. 1 = data toggle synchronization is performed 0 = no data toggle synchronization is performed bit 2: bstall: buffer stall setting this bit will cause the usb to issue a stall handshake if a token is received by the sie that would use the bd in this location. the bd is not consumed by the sie (the own bit remains and the rest of the bd are unchanged) when a bstall bit is set. bit 1-0: reserved: read as ? x ? note: recommend that users not use bsf, bcf due to the dual functionality of this register. 745cov.book page 69 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 70 preliminary ? 2000 microchip technology inc. register 10-11: buffer descriptor status. bits read by the mcu (bdndst: 1a0h, 1a4h, 1a8h, 1ach, 1b0h, 1b4h) register 10-12: buffer descriptor byte count (bdndbc: 1a1h, 1a5h, 1a9h, 1adh, 1b1h, 1b5h) r/w-0 r/w-x r/w-x r/w-x r/w-x r/w-x u-x u-x uown data0/1 pid3 pid2 pid1 pid0 ? ? r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset x = don ? t care bit7 bit0 bit 7: uown: usb own this uown bit determines who currently owns the buffer. the sie writes a 0 to this bit when it has com- pleted a token. this byte of the bd should always be the last byte the mcu updates when it initializes a bd. once the bd has been assigned to the usb, the mcu should not change it in any way. 1 = usb has exclusive access to the bd. the mcu should not modify the bd or buffer. 0 = the mcu has exclusive access to the bd. the usb ignores all other fields in the bd. bit 6: data0/1: this bit defines the type of data toggle packet that was transmitted or received 1 = data 1 packet 0 = data 0 packet bit 5-2: pid<3:0>: packet identifier the received token pid value. bit 1-0: reserved: read as 'x' note: recommend that users not use bsf, bcf due to the dual functionality of this register. u-x u-x u-x u-x r/w-x r/w-x r/w-x r/w-x ? ? ? ? bc3 bc2 bc1 bc0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset x = don ? t care bit7 bit0 bit 7-4: reserved: read as ? x ? bit 3-0: bc<3:0>: the byte count bits represent the number of bytes that will be transmitted for an in token or received during an out token. valid byte counts are 0 - 8. the sie will change this field upon the com- pletion of an out or setup token with the actual byte count of the data received. 745cov.book page 70 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 71 pic16c745/765 register 10-13: buffer descriptor address low (bdndal: 1a2h, 1a6h, 1aah, 1aeh, 1b2h, 1b6h) 10.6.1 endpoint buffers endpoint buffers are located in the dual port ram area. the starting location of an endpoint buffer is determined by the buffer descriptor. 10.7 transceiver an on-chip integrated transceiver is included to drive the d+/d- physical layer of the usb. 10.7.1 regulator a 3.3v regulator provides the d+/d- drives with power, as well as an external pin. this pin is intended to be used to power a 1.5k ? + 5% pull-up resistor on the d- line to signal a low speed device, as specified by the usb 1.1 specification. a + 20% 200nf capacitor is required on v usb for regulator stability. figure 10-2: external circuitry 10.7.1.1 v usb output the v usb provides a 3.3v nominal output. this drive current is sufficient for a pull-up only. 10.8 usb software libraries microchip technology provides a comprehensive set of chapter 9 standard requests functions to aid devel- opers in implementing their designs. see microchip technology ? s website for the latest version of the soft- ware libraries. table 10-1: usb port functions r/w-xr/w-xr/w-xr/w-xr/w-xr/w-xr/w-xr/w-x ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? -n = value at por reset x = don ? t care bit7 bit0 bit 7-0: ba<7:0>: buffer address the base address of the buffer controlled by this endpoint. the upper order bit address (ba8) of the 9-bit address is assumed to be 1h. this value must point to a location within the dual port memory space, bank 3 (1b8h - 1dfh). note 1: this register should always contain a value between b8h-dfh. pic16c745/765 host controller/hub v usb d- d+ 200 nf application note: the pic16c745/765 requires an external resistor and capacitor to communicate with a host over usb. 1.5k name function input type output type description v usb v usb ? power regulator output voltage d- d- usb usb usb differential bus d+ d+ usb usb usb differential bus legend: od = open drain, st = schmitt trigger 745cov.book page 71 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 72 preliminary ? 2000 microchip technology inc. 10.9 usb firmware users guide 10.9.1 introducing the usb software interface microchip provides a layer of software that handles the lowest level interface so your application won ? t have to. this provides a simple put/get interface for com- munication. most of the usb processing takes place in the background through the interrupt service routine. from the application viewpoint, the enumeration pro- cess and data communication takes place without fur- ther interaction. however, substantial setup is required in the form of generating appropriate descriptors. figure 10-3: usb software interface 10.9.2 integrating usb into your application the latest version of the usb interface software is available on microchip's website (see http://www.microchip.com/). the interface to the application is packaged in 3 func- tions: initusb, putusb and getusb . initusb initial- izes the usb peripheral, allowing the host to enumerate the device. then, for normal data commu- nications, function putusb sends data to the host and getusb receives data from the host. however, there's a fair amount of setup work that must be completed. usb depends heavily on the descrip- tors. these are the software parameters that are com- municated to the host to let it know what the device is, and how to communicate with it. see usb v1.1 spec section 9.5 for more details. also, code must be added to give meaning to the setconfiguration command. the chapter 9 com- mands call setconfiguration when it receives the command. both the descriptors and setconfigura- tion are in descript.asm . initusb enables the usb interrupt so enumeration can begin. the actual enumeration process occurs in the background, driven by the host and the interrupt service routine. macro configuredusb waits until the device is in the configured state. the time required to enumerate is completely dependent on the host and bus loading. 10.9.3 interrupt structure concerns 10.9.3.1 processor resources most of the usb processing occurs via the interrupt and thus is invisible to application. however, it still con- sumes processor resources. these include rom, ram, common ram and stack levels. this section attempts to quantify the impact on each of these resources, and shows ways to avoid conflicts. if you write your own interrupt service routine: w, status, fsr and pclath may be corrupted by servic- ing the usb interrupt and must be saved. usb_main.asm provides a skeleton isr which does this for you, and includes tests for each of the possible interrupt bits. this provides a good starting point if you haven't already written your own. 10.9.3.2 stack levels the hardware stack on the picmicro ? mcu is only 8 levels deep. so the worst case call between the applica- tion and isr can only be 8 levels. the enumeration pro- cess requires 4 levels, so it ? s best if the main application holds off on any processing until enumeration is com- plete. configuredusb is a macro that waits until the enumeration process is complete for exactly this pur- pose, by testing the lower two bits of uswstat ( 0x197 ). 10.9.3.3 rom the code required to support the usb interrupt, including the chapter 9 interface calls, but not includ- ing the descriptor tables, is about 1kw. the descriptor and string descriptor tables can each take up to an additional 256w. the location of these parts is not restricted. 10.9.3.4 ram with the exception of common ram discussed below, servicing the usb interrupt requires ~40 bytes of ram in bank 2. that leaves all the general purpose ram in banks zero and one, plus half of bank two, available for your application to use. 10.9.3.5 common ram usage the pic16c745/765 has 16 bytes of common ram. these are the last 16 addresses in each bank and all refer to the same 16 bytes of memory, without regard to which register bank is currently addressed by the rp0, rp1 and irp bits. these are particularly useful when responding to inter- rupts. when an interrupt occurs, the isr doesn ? t imme- diately know which bank is addressed. with devices that don ? t support common ram, the w register must be provided for in each bank. the 16c745/765 can save the appropriate registers in common ram and not have to waste a byte in each bank for w register. main application put get init usb peripheral usb usb usb usb 745cov.book page 72 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 73 pic16c745/765 10.9.3.6 buffer allocation the pic16c745/765 has 64 bytes of dual port ram. 24 are used for the buffer descriptor table (bdt), leaving 40 bytes for buffers. endpoints 0 in and out need dedicated buffers since a setup transaction can never be naked. that leaves three buffers for four possible endpoints, but the usb spec requires that low speed devices are only allowed 2 endpoints (usb 1.1 paragraph 5.3.1.2), where an endpoint is a simplex connection that is defined by the combination of endpoint number and direction. 10.9.3.7 vendor specific commands vendor specific commands are defined by the vendor. these are parsed out, but are not processed. instead, control is passed to function checkvendor where they can be processed. 10.9.4 file packaging the software interface is packaged into four files, designed to simplify the integration with your application. file usb_ch9.asm contains the interface and core functions needed to enumerate the bus. descript.asm contains the device, config, inter- face, endpoint and string descriptors. both of these files must be linked in with your application. hidclass.asm provides some hid class specific functions. currently only getreportdescriptor is sup- ported. other class specific functions can be imple- mented in a similar fashion. when a token done interrupt determines that it ? s a class specific command on the basis that reporttype bit 6 is set, control is passed to function classspecific . if you ? re working with a different class, this is your interface between the core functions and the class specific functions. usb_main.asm is useful as a starting point on a new application and as an example of how an existing application needs to service the usb interrupt and communicate with the core functions. 10.9.5 function call reference interface between the application and protocol layer takes place in three main functions: initusb, putusb and getusb . initusb should be called by the main program immedi- ately upon power-up. it enables the usb peripheral and usb reset interrupt, and transitions the part to the pow- ered state to prepare the device for enumeration. see section 10.9.6 ? behind the scenes ? for details on the enumeration process. deinitusb disables the usb peripheral, removing the device from the bus. an application might call deinitusb if it was finished communicating to the host and didn't want to be polled any more. putusb (buffer pointer, buffer size, endpoint) sends data up to the host. the pointer to the block of data to transmit is in the fsr/irp, and the block size and end- point is passed in w register. if the in buffer is available for that endpoint, putusb copies the buffer, flips the data 0/1 bit and sets the owns bit. a buffer not avail- able would occur when it has been previously loaded and the host has not requested that the usb peripheral transmit it. in this case, a failure code would be returned so the application can try again later. getusb (buffer pointer, endpoint) returns data sent from the host. if the out buffer pointed to by the endpoint number is ready, as indicated by the owns bit, the buffer is copied from dual port ram to the locations pointed to by the buffer pointer, and resets the endpoint for the next out transaction from the host. if no data is available, it returns a failure code. thus the functions of polling for buffer ready and copying the data are com- bined into the one function. serviceusbint handles all interrupts generated by the usb peripheral. first, it copies the active buffer to com- mon ram, which provides a quick turn around on the buffer in dual port ram and also avoids having to switch banks during processing of the buffer. file usb_main.asm gives an example of how serviceusbint would be invoked. stallusbep/unstallusbep sets or clears the stall bit in the endpoint control register. the stall bit indicates to the host that user intervention is required and until such intervention is made, further attempts to communicate with the endpoint will not be successful. once the user intervention has been made, unstallusbep clears the bit allowing communication to take place. these calls are useful to signal to the host that user intervention is required. an example of this might be a printer out of paper. softdetachusb clears the dev_att bit, electrically disconnecting the device from the bus, then reconnect- ing, so it can be re-enumerated by the host. this pro- cess takes approximately 50 ms, to ensure that the host has seen the device disconnect and reattach to the bus. checksleep tests the uctrl.uidle bit if set, indicat- ing that there has been no activity on the bus for 3 ms. if set, the device can be put to sleep, which puts the part into a low power standby mode, until wakened by bus activity. this has to be handled outside the isr because we need the interrupt to wake us from sleep, and also because the application may not be ready to sleep when the interrupt occurs. instead, the applica- tion should periodically call this function to poll the bit, when the device is in a good place to sleep. prior to putting the device to sleep, it enables the activity interrupt so the device will be awakened by the first transition on the bus. the picmicro device will immediately jump to the isr, recognize the activity interrupt, which then disables the interrupt and resumes processing with the instruction following the checksleep call. 745cov.book page 73 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 74 preliminary ? 2000 microchip technology inc. configuredusb (macro) continuously polls the enu- meration status bits and waits until the device has been configured by the host. this should be used after the call to initusb and prior to the first time your application attempts to communicate on the bus. setconfiguration is a callback function that allows your application to associate some meaning to a set configuration command from the host. the ch9 soft- ware stores the value in usb_curr_config so it can be reported back on a get configuration call. this func- tion is also called, passing the new configuration in w. this function is called from within the isr, so it should be kept as short as possible. 10.9.6 behind the scenes initusb clears the error counters and enables the 3.3v regulator and the usb reset interrupt. this implements the requirement to prevent the picmicro device from responding to commands until the device has been reset. the host sees the device and resets the device, to begin the enumeration process. the reset then ini- tializes the buffer descriptor table (bdt), endpoint control registers and enables the remaining usb interrupt sources. the interrupt transfers control to the interrupt vector (address 0x0004 ). any interrupt service routine must preserve the processor state by saving the fsrs that might change during interrupt processing. we rec- ommend saving w, status, pclath and fsr. w can be stored in unbanked ram to avoid banking issues. then it starts polling the interrupt flags to see what triggered the interrupt. the usb interrupts are serviced by calling serviceusbint which further tests the usb interrupt sources to determine how to pro- cess the interrupt. then, the host sends a setup token requesting the device descriptor. the usb peripheral receives the setup transaction, places the data portion in the ep0 out buffer, loads the ustat register to indicate which endpoint received the data and triggers the token done (tok_dne) interrupt. the chapter 9 commands then interpret the setup token and sets up the data to respond to the request in the ep0 in buffer, then sets the uown bit to tell the sie there is data available. then, the host sends an in transaction to receive the data from the setup transaction. the sie sends the data from the ep0 in buffer and then sets the token done interrupt to notify us that the data has been sent. if there is additional data, the next buffer is setup in ep0 in buffer. this token processing sequence holds true for the entire enumeration sequence, which walks through the flow chart starting chapter 9 of the usb spec. the device starts off in the powered state, transitions to default via the reset interrupt, transitions to addressed via the setaddress command, and transitions to configured via a setconfiguration command. the usb peripheral detects several different errors and handles most internally. the usb_err interrupt notifies the picmicro device that an error has occurred. no action is required by the device when an error occurs. instead, the errors are simply acknowl- edged and counted. there is no mechanism to pull the device off the bus if there are too many errors. if this behavior is desired, it must be implemented in the application. the activity interrupt is left disabled until the usb peripheral detects no bus activity for 3 ms. then it suspends the usb peripheral and enables the activity interrupt. the activity interrupt then reactivates the usb peripheral when bus activity resumes, so pro- cessing may continue. checksleep is a separate call that takes the bus idle one step further and puts the picmicro device to sleep, if the usb peripheral has detected no activity on the bus. this powers down most of the device to minimal current draw. this call should be made at a point in the main loop where all other processing is complete. 745cov.book page 74 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 75 pic16c745/765 10.9.7 example this example shows how the usb functions are used. this example first initializes the usb peripheral, which allows the host to enumerate the device. the enumer- ation process occurs in the background, via an inter- rupt service routine. this function waits until enumeration is complete, and then polls ep1 out to see if there is any data available. when a buffer is available, it is copied to the in buffer. presumably your application would do something more interesting with the data than this example. ; ****************************************************************** ; demo program that initializes the usb peripheral, allows the host ; to enumerate, then copies buffers from ep1out to ep1in. ; ****************************************************************** main call initusb ; set up everything so we can enumerate configuredusb ; wait here until we have enumerated. checkep1 ; check endpoint 1 for an out transaction bankisel buffer ; point to lower banks movlw buffer movwf fsr ; point fsr to our buffer movlw 1 ; check end point 1 call getusb ; if data is ready, it will be copied. btfss status,c ; was there any data for us? goto putbuffer ; nope, check again. ; code host to process out buffer from host putbuffer bankisel buffer ; point to lower banks ; save buffer length movlw buffer movwf fsr ; point fsr to our buffer movlw 0x81 ; put 8 bytes to endpoint 1 call putusb btfss status,c ; was it successful? goto putbuffer ; no: try again until successful goto idleloop ; yes: restart loop end 10.9.8 assembling the code the code is designed to be used with the linker. there is no provision for includable files. the code comes packaged as several different files: usb_ch9.asm - handles all the chapter 9 com- mand processing. usb_defs.inc - #defines used throughout the code. usb_main.asm - sample interrupt service routine. hidclass.asm - handles the hid class specific commands. 10.9.8.1 assembly options there are two #defines at the top of the code that con- trol assembly options. 10.9.8.2 #define errorcounters this define includes code to count the number of errors that occur, by type of error. this requires extra code and ram locations to implement the counters. 10.9.8.3 #define functionids this is useful for debug. it encodes the upper 6 bits of uswstat (0x197) to indicate which function is exe- cuting. see the defines in usb_defs.inc for the codes that will be encoded. 745cov.book page 75 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 76 preliminary ? 2000 microchip technology inc. notes: 745cov.book page 76 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 77 pic16c745/765 11.0 universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci). the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a inte- grated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) bits spen (rcsta<7>) and trisc<7:6> have to be set in order to configure pins rc6/tx/ck and rc7/rx/ dt as the universal synchronous asynchronous receiver transmitter. register 11-1: transmit status and control register (txsta: 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7: csrc : clock source select bit asynchronous mode don ? t care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6: tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4: sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3: unimplemented: read as '0' bit 2: brgh : high baud rate select bit asynchronous mode 1 = high speed 0 = low speed synchronous mode unused in this mode bit 1: trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data. (can be used for parity.) 745cov.book page 77 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 78 preliminary ? 2000 microchip technology inc. register 11-2: receive status and control register (rcsta: 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ? ferr oerr rx9d r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7: spen : serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6: rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit asynchronous mode don ? t care synchronous mode - master 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave unused in this mode bit 4: cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3: unimplemented: read as '0' bit 2: ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0: rx9d : 9th bit of received data. (can be used for parity.) 745cov.book page 78 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 79 pic16c745/765 11.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 11-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and f int , the nearest inte- ger value for the spbrg register can be calculated using the formula in table 11-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f int /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 11.1.1 sampling the data on the rc7/rx/dt pin is sampled three times near the center of each bit time by a majority detect cir- cuit to determine if a high or a low level is present at the rx pin. table 11-1: baud rate formula table 11-2: baud rates for synchronous mode table 11-3: baud rates for asynchronous mode (brgh = 0) sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f int /(64(spbrg+1)) (synchronous) baud rate = f int /(4(spbrg+1)) baud rate = f int /(16(spbrg+1)) na desired baud 24 mhz actual baud % of error spbrg 300 ?? ? 1200 ?? ? 2400 ?? ? 4800 ?? ? 9600 ?? ? 19200 ?? ? 38400 38461.54 0.16 155 57600 57692.31 0.16 103 115200 115384.62 0.16 51 230400 230769.23 0.16 25 460800 461538.46 0.16 12 921600 1000000.00 8.51 5 desired baud 24 mhz actual baud % of error spbrg 300 ??? 1200 ??? 2400 2403.85 0.16 155 4800 4807.69 0.16 77 9600 9615.38 0.16 38 19200 19736.84 2.80 18 38400 41666.67 8.51 8 57600 62500.00 8.51 5 115200 125000.00 8.51 2 230400 ??? 460800 ??? 921600 ??? 745cov.book page 79 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 80 preliminary ? 2000 microchip technology inc. table 11-4: baud rates for asynchronous mode (brgh = 1) table 11-5: registers associated with baud rate generator desired baud 24 mhz actual baud % of error spbrg 300 ??? 1200 ??? 2400 ??? 4800 ??? 9600 9615.38 0.16 155 19200 19230.77 0.16 77 38400 38461.54 0.16 38 57600 57692.31 0.16 25 115200 115384.62 0.16 12 230400 250000.00 8.51 5 460800 500000.00 8.51 2 921600 ??? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg. 745cov.book page 80 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 81 pic16c745/765 11.2 u sart asynchronous mode in this mode, the usart uses standard nonreturn-to- zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data format is 8 bits. an on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the usart ? s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 11.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 11-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by setting/clearing enable bit txie ( pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicated the sta- tus of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. sta- tus bit trmt is a read only bit, which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 11-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 11-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rc6/tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. figure 11-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ? 745cov.book page 81 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 82 preliminary ? 2000 microchip technology inc. steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 11.1) 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 11-2: asynchronous master transmission figure 11-3: asynchronous master transmission (back to back) table 11-6: registers associated with asynchronous transmission address name b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 745cov.book page 82 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 83 pic16c745/765 11.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 11-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f int . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, flag bit rcif (pir1<5>) is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e., it is a two deep fifo. it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, then overrun error bit oerr (rcsta<1>) will be set. the word in the rsr will be lost. the rcreg reg- ister can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in software. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhibited, so it is essential to clear error bit oerr if it is set. fram- ing error bit ferr (rcsta<2>) is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg, will load bits rx9d and ferr with new values, therefore it is essential for the user to read the rcsta register before reading rcreg register in order not to lose the old ferr and rx9d information. figure 11-4: usart receive block diagram figure 11-5: asynchronous reception spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. 745cov.book page 83 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 84 preliminary ? 2000 microchip technology inc. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 11.1). 2. enable the asynchronous serial port by clearing bit sync, and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. table 11-7: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. 745cov.book page 84 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 85 pic16c745/765 11.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner, i.e., transmission and reception do not occur at the same time. when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 11.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 11-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg is empty and inter- rupt bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 11-6). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 11-7). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen, during a transmission, will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to hi- impedance. if either bit cren or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a hi-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting, since bit txen is still set. the dt line will immediately switch from hi-imped- ance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ? new ? tx9d, the ? present ? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 11.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 745cov.book page 85 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 86 preliminary ? 2000 microchip technology inc. table 11-8: registers associated with synchronous master transmission figure 11-6: synchronous transmission figure 11-7: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? note: sync master mode; spbrg = ? 0 ? . continuous transmission of two 8-bit words. word 2 trmt bit write word1 write word2 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit 745cov.book page 86 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 87 pic16c745/765 11.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>) or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the recep- tion is continuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit rcif (pir1<5>) is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit, which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e., it is a two deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value, therefore it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate (section 11.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 11-9: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. 745cov.book page 87 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 88 preliminary ? 2000 microchip technology inc. figure 11-8: synchronous reception (master mode, sren) cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = ? 1 ? and bit brg = ? 0 ? . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ? 0 ? q1 q2 q3 q4 745cov.book page 88 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 89 pic16c745/765 11.4 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 11.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the inter- rupt vector (0004h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 11.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. also, bit sren is a don ? t care in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 745cov.book page 89 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 90 preliminary ? 2000 microchip technology inc. table 11-10: registers associated with synchronous slave transmission table 11-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the pic16c745; always maintain these bits clear. 745cov.book page 90 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 91 pic16c745/765 12.0 analog-to-digital converter (a/d) module the 8-bit analog-to-digital (a/d) converter module has five inputs for the pic16c745 and eight for the pic16c765. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital value. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltage is software selectable to either the device ? s positive supply voltage (v dd ) or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d ? s dedicated internal rc oscillator. the a/d module has three registers. these registers are: a/d result register (adres) a/d control register 0 (adcon0) a/d control register 1 (adcon1) the adcon0 register, shown in register 12-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 12-2, configures the func- tions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference) or as digital i/o. additional information on using the a/d module can be found in the picmicro ? mid-range mcu family ref- erence manual (ds33023) and in application note, an546. note: in order to maintain 8-bit a/d accuracy, adcs<1:0> must be set to either f int /32 or f rc . choosing f int /8 or f int /2 will cause loss of accuracy, due to the usb module ? s requirement of running at 24 mhz. 745cov.book page 91 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 92 preliminary ? 2000 microchip technology inc. register 12-1: a/d control register (adcon0: 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ? adon r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset bit7 bit0 bit 7-6: adcs<1:0>: a/d conversion clock select bits 00 = f int /2 01 = f int /8 10 = f int /32 (2) 11 = f rc (clock derived from dedicated internal oscillator) (2) bit 5-3: chs<2:0> : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) 101 = channel 5, (re0/an5) (1) 110 = channel 6, (re1/an6) (1) 111 = channel 7, (re2/an7) (1) bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current note 1: a/d channels 5, 6 and 7 are implemented on the pic16c765 only. 2: choose f int /32 or f rc to maintain 8-bit a/d accuracy at 24 mhz. 745cov.book page 92 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 93 pic16c745/765 register 12-2: a/d control register 1 (adcon1: 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n =value at por reset bit7 bit0 bit 7-3: unimplemented: read as '0' bit 2-0: pcfg<2:0>: a/d port configuration control bits note 1: a/d channels 5, 6 and 7 are implemented on the pic16c765 only. a = analog input d = digital i/o pcfg<2:0> an7 (1) an6 an5 an4 an3 an2 an1 an0 v ref 000 a aaaaaaav dd 001 aaaav ref aaara3 010 d ddaaaaav dd 011 dddav ref aaaan3 100 d dddadaav dd 101 aaaav ref aaaan3 11x d dddddddv dd 745cov.book page 93 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 94 preliminary ? 2000 microchip technology inc. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: configure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 12-1: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg<2:0> chs<2:0> 000 or 010 or 100 or 001 or 011 or 101 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: not available on pic16c745. 11x 745cov.book page 94 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 95 pic16c745/765 12.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 12-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), figure 12-2. the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for ana- log sources is 10 k ? . after the analog input channel is selected (changed), the acquisition must pass before the conversion can be started. to calculate the minimum acquisition time, equation 12-1 may be used. this equation assumes that 1/2 lsb error is used (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range mcu family reference manual (ds33023). in general, however, given a max of 10k ? and a worst case temperature of 100 c, t acq will be no more than 16sec. figure 12-2: analog input model equation 12-1: acquisition time c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions t acq = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff t amp = 5 s t c = - (51.2pf)(1k ? + r ss + r s ) in(1/511) t coff = (temp -25 c)(0.05 s/ c) 745cov.book page 95 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 96 preliminary ? 2000 microchip technology inc. 12.2 s electing the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.5t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: 2t osc 8t osc 32t osc dedicated internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 12-1: t ad vs. device operating frequencies 12.3 c onfiguring analog port pins the adcon1, trisa and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<2:0> bits and the tris bits. 12.4 a /d conversion s clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d con- version sample. that is, the adres register will con- tinue to contain the value of the last completed conversion (or the last value written to the adres reg- ister). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, an acquisition is automatically started on the selected channel. 12.5 a /d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs<1:0> = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the con- version is completed, the go/done bit will be cleared, and the result loaded into the adres regis- ter. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 12.6 e ffects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all pins with analog functions are configured as available inputs. the adres register will contain unknown data after a power-on reset. ad clock source (t ad ) device frequency operation adcs1:adcs0 24 mhz 2t osc 00 83.3 ns 8t osc 01 333.3 ns 32t osc 10 1.333 rc 11 2 - 6 s (1,2) note 1: the rc source has a typical t ad time of 4 s. 2: for device frequencies above 1 mhz, the device must be in sleep for the entire con- version, or the a/d accuracy may be out of specification. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the input buffer to consume current that is out of specification. 3: the trise register is not provided on the pic16c745. note: the go/done bit should not be set in the same instruction that turns on the a/d. note: for the a/d module to operate in sleep , the a/d clock source must be set to rc (adcs<1:0> = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruc- tion that sets the go/done bit. 745cov.book page 96 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 97 pic16c745/765 12.7 use of the ccp trigger an a/d conversion can be started by the ? special event trigger ? of the ccp2 module. this requires that the ccp2m<3:0> bits (ccp2con<3:0>) be programmed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ? special event trigger ? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ? special event trigger ? will be ignored by the a/d module, but will still reset the timer1 counter. table 12-2: summary of a/d registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif usbif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie usbie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done ? adon 0000 00-0 0000 00-0 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 09h porte ? ? ? ? ? re2 (1) re1 (1) re0 (1) ---- -xxx ---- -uuu 89h trise ibf (1) obf (1) ibov (1) psp-mode (1) ? porte (1) data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: these bits are reserved on the pic6c745; always maintain these bits clear. 745cov.book page 97 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 98 preliminary ? 2000 microchip technology inc. notes: 745cov.book page 98 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 99 pic16c745/765 13.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real- time applications. the pic16c745/765 family has a host of such features intended to maximize system reli- ability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming ? (icsp) the pic16c745/765 has a watchdog timer, which can be shut off only through configuration bits. it runs off its own dedicated rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is sta- ble. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only and is designed to keep the part in reset, while the power supply stabilizes. with these two timers on- chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, wdt wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the ec oscillator allows the user to directly drive the microcon- troller, while the hs oscillator allows the use of a high speed crystal/resonator. a set of configuration bits are used to select various options. 13.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h - 3fffh), which can be accessed only during programming. register 13-1: configuration word cp1 cp0 cp1 cp0 cp1 cp0 ? ? cp1 cp0 pwrte wdte fosc1 fosc0 register: config address 2007h bit13 bit0 bit 13-12: cp<1:0>: code protection bits (1) 11-10: 00 = all memory is code protected 9-8: 01 = upper 3/4th of program memory code protected 5-4: 10 = upper half of program memory code protected 11 = code protection off bit 7-6: unimplemented: read as ? 1 ? bit 3: pwrte : power-up timer enable bit 1 = pwrt disabled no delay after power-up reset or brown-out reset 0 = pwrt enabled a delay of 4x wdt (72 ms) is present after power-up and brown-out bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc<1:0>: oscillator selection 00 = hs - hs osc 01 = ec - external clock. clkout on osc2 pin 10 = h4 - hs osc with 4x pll enabled 11 = e4 - external clock with 4x pll enabled. clkout on osc2 pin note 1: all of the cp<1:0> pairs have to be given the same value to enable the code protection scheme listed. 745cov.book page 99 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 100 preliminary ? 2000 microchip technology inc. 13.2 o scillator configurations 13.2.1 oscillator types the pic16c745/765 can be operated in four different oscillator modes. the user can program a configuration bit (fosc0) to select one of these four modes: ec external clock e4 external clock with internal pll enabled hs high speed crystal/resonator h4 high speed crystal/resonator with internal pll enabled 13.2.2 crystal oscillator/ceramic resonators in hs mode, a crystal or ceramic resonator is con- nected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 13-1). the pic16c745/ 765 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in hs mode, the device can have an external clock source to drive the osc1/clkin pin (figure 13-2). in this mode, the oscillator start-up timer is active for a period of 1024*t osc . see the picmicro ? mid-range mcu reference manual (ds33023) for details on building an external oscillator. figure 13-1: crystal/ceramic resonator operation (hs osc configuration) table 13-1: ceramic resonators table 13-2: capacitor selection for crystal oscillator 13.2.3 h4 mode in h4 mode, a pll module is switched on in-line with the clock provided across osc1 and ocs2. the output of the pll drives f int . 13.2.4 pll an on-board 4x pll provides a cheap means of gener- ating a stable 24 mhz f int , using an external 6 mhz resonator. after power-up, a pll settling time of less than t pllrt is required. c1 c2 xtal osc2 note1 osc1 rf sleep to internal logic pic16c745/765 rs note 1: a series resistor may be required for at strip cut crystals. ranges tested: mode freq osc1 osc2 hs 6.0 mhz 10 - 68 pf 10 - 68 pf these values are for design guidance only. see notes at bottom of page. osc type crystal freq cap. range c1 cap. range c2 hs 6.0 mhz 15 - 33 pf 15 - 33 pf these values are for design guidance only. see notes at bottom of page. note 1: higher capacitance increases the stability of the oscillator, but also increases the start- up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 3: rs may be required in hs mode to avoid overdriving crystals with low drive level specification. 4: when migrating from other picmicro devices, oscillator performance should be verified. 5: users should consult the usb specification 1.1 to ensure their resonator/crystal oscilla- tor meets the required jitter limits for usb operation. 745cov.book page 100 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 101 pic16c745/765 13.2.5 external clock in in ec mode, users may directly drive the pic16c745/ 765 provided that this external clock source meets the ac/dc timing requirements listed in section 17.4. figure 13-2 below shows how an external clock circuit should be configured. figure 13-2: external clock input operation (ec osc configuration) 13.2.6 e4 mode in e4 mode, a pll module is switched on in-line with the clock provided to osc1. the output of the pll drives f int . figure 13-3: oscillator/pll clock control 13.3 r eset the pic16cxx differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (normal operation) brown-out reset (bor) some registers are not affected in any reset condi- tion; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ? reset state ? on por, on the mclr and wdt reset, on mclr reset during sleep, and on bor. the to and pd bits are set or cleared differently in different reset situations as indicated in table 13-4. these bits are used in software to determine the nature of the reset. see table 13-7 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 13-4. the picmicro ? devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. clock from ext. system pic16c745/765 osc1 osc2/clkout clkout note: clkout is the same frequency as osc1 if in e4 mode, otherwise clkout = osc1/4. osc2 osc1 ec e4 hs h4 4x pll 6 mhz q clock generator to circuits 24 mhz f int ec e4 hs h4 745cov.book page 101 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 102 preliminary ? 2000 microchip technology inc. figure 13-4: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt dedicated rc osc time-out power-on reset ost 10-bit ripple counter pwrt chip reset 10-bit ripple counter reset enable ost enable pwrt sleep brown-out reset on-chip 745cov.book page 102 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 103 pic16c745/765 13.4 resets 13.4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will elimi- nate external rc components usually needed to create a por. a maximum rise time for v dd is specified. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the startup conditions. for additional information, refer to application note an607, ? power-up trouble shooting . ? 13.4.2 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up from the por. the pwrt oper- ates on an internal rc oscillator. the device is kept in reset as long as the pwrt is active. the pwrt ? s time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameters for details (t pwrt , parameter #33). 13.4.3 oscillator start-up timer (ost) the oscillator start-up timer provides a delay of 1024 oscillator cycles (from osc1 input) after the pwrt delay. this ensures that the crystal oscillator or resona- tor has started and stabilized. the ost time-out is invoked only for hs mode and only on power-on reset or wake-up from sleep. 13.4.4 brown-out reset (bor) if v dd falls below v bor (parameter d005) for longer than t bor (parameter #35), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33). if v dd should fall below v bor during t pwrt , the brown-out reset process will restart when v dd rises above v bor , with the power- up timer reset. since the device is intended to oper- ate at 5v nominal only, the brown-out detect is always enabled and the device will reset when vdd falls below the brown-out threshold. this device is unique in that the 4 ? wdt timer will not activate after a brown- out if pwrte = 1 (inactive). 13.4.5 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled), when a power-on reset occurs. then ost starts counting 1024 oscillator cycles when pwrt ends (hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution imme- diately. this is useful for testing purposes or to synchro- nize more than one pic16cxx device operating in parallel. table 13-5 shows the reset conditions for the sta- tus, pcon and pc registers, while table 13-7 shows the reset conditions for all the registers. 13.4.6 power control/status register (pcon) the brown-out reset status bit, bor , is unknown on a por. it must be set by the user and checked on sub- sequent resets to see if bit bor was cleared, indi- cating a bor occurred. the bor bit is not predictable if the brown-out reset circuitry is disabled. the power-on reset status bit, p or , is cleared on a por and unaffected otherwise. the user must set this bit following a por and check it on subsequent resets to see if it has been cleared. 745cov.book page 103 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 104 preliminary ? 2000 microchip technology inc. 13.5 time-out in various situations table 13-3: reset time-outs table 13-4: status bits and their significance table 13-5: reset condition for special registers oscillator configuration por bor wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 hs t pwrt + 1024 ? t osc 1024 ? t osc t pwrt + 1024 ? t osc 1024 ? t osc 1024 ? t osc h4 t pwrt + t pllrt + 1024 ? t osc t pllrt + 1024 ? t osc t pwrt + t pllrt + 1024 ? t osc t pllrt + 1024 ? t osc t pllrt + 1024 ? t osc ec t pwrt 0t pwrt 00 e4 t pwrt + t pllrt t pllrt t pwrt + t pllrt t pllrt t pllrt por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 000x xuuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as ? 0 ? . note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). table 13-6: registers associated with resets address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 03h, 83h, 103h, 183h status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 8eh pcon ? ? ? ? ? ? por bor ---- --qq ---- --uu legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. 745cov.book page 104 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 105 pic16c745/765 table 13-7: initialization conditions for all registers register power-on reset brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta --0x 0000 --0u 0000 --uu uuuu portb xxxx xxxx uuuu uuuu uuuu uuuu portc xx-- -xxx uu-- -uuu uu-- -uuu portd (4) xxxx xxxx uuuu uuuu uuuu uuuu porte (4) ---- -xxx ---- -uuu ---- -uuu pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 0000 0000 0000 0000 uuuu uuuu (1) pir2 ---- ---0 ---- ---0 ---- ---u (1) tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con --00 0000 --uu uuuu --uu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu rcsta 0000 -00x 0000 -00x uuuu -uuu txreg 0000 0000 0000 0000 uuuu uuuu rcreg 0000 0000 0000 0000 uuuu uuuu ccpr2l xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 0000 0000 0000 0000 uuuu uuuu adres xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u option_reg 1111 1111 1111 1111 uuuu uuuu trisa --11 1111 --11 1111 --uu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisc 11-- -111 11-- -111 uu-- -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 13-5 for reset value for specific condition. 4: pic16c765 only. 745cov.book page 105 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 106 preliminary ? 2000 microchip technology inc. trisd (4) 1111 1111 1111 1111 uuuu uuuu trise (4) 0000 -111 0000 -111 uuuu -uuu pie1 0000 0000 0000 0000 uuuu uuuu pie2 ---- ---0 ---- ---0 ---- ---u pcon ---- --0q (3) ---- --uu ---- --uu pr2 1111 1111 1111 1111 1111 1111 txsta 0000 -010 0000 -010 uuuu -uuu spbrg 0000 0000 0000 0000 uuuu uuuu adcon1 ---- -000 ---- -000 ---- -uuu uir --00 0000 --00 0000 --00 0000 uie --00 0000 --00 0000 --00 0000 ueir 0000 0000 0000 0000 0000 0000 ueie 0000 0000 0000 0000 0000 0000 ustat ---x xx-- ---u uu-- ---u uu-- uctrl --x0 000- --xq qqq- --xq qqq- uaddr -000 0000 -000 0000 -000 0000 uswstat 0000 0000 0000 0000 0000 0000 uep0 ---- 0000 ---- 0000 ---- 0000 uep1 ---- 0000 ---- 0000 ---- 0000 uep2 ---- 0000 ---- 0000 ---- 0000 table 13-7: initialization conditions for all registers (continued) register power-on reset brown-out reset mclr resets wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 13-5 for reset value for specific condition. 4: pic16c765 only. 745cov.book page 106 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 107 pic16c745/765 13.6 i nterrupts the interrupt control register (intcon) records individ- ual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all unmasked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupt ? s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the ? return from interrupt ? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2 and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit or the gie bit. note: if an interrupt occurs while the global interrupt enable (gie) bit is being cleared, the gie bit may unintentionally be re- enabled by the user ? s interrupt service routine (the retfie instruction). the events that would cause this to occur are: 1. an instruction clears the gie bit while an interrupt is acknowledged. 2. the program branches to the inter- rupt vector and executes the interrupt service routine. 3. the interrupt service routine com- pletes the execution of the retfie instruction. this causes the gie bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to dis- able interrupts. perform the following to ensure that inter- rupts are globally disabled: loop bcf intcon, gie ; disable global ; interrupt bit btfsc intcon, gie ; global interrupt ; disabled? goto loop ; no, try again : ; yes, continue ; with program ; flow 745cov.book page 107 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 108 preliminary ? 2000 microchip technology inc. figure 13-5: wake-up from sleep through interrupt figure 13-6: interrupt logic q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc+2 interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed processor in sleep note 1: hs oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay is not present in ec osc mode. 3: gie = ? 1 ? assumed. after wake-up, the processor jumps to the interrupt routine. if gie = ? 0 ? , execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. pspif (1) pspie (1) adif adie rcif rcie txif txie usbif usbie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if the following table shows the interrupts for each device. note 1: pic16c765 only. device t0if intf rbif pspif adif rcif txif usbif ccp1if tmr2if tmr1if ccp2if pic16c745 yes yes yes ? yes yes yes yes yes yes yes yes pic16c765 yes yes yes yes yes yes yes yes yes yes yes yes 745cov.book page 108 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 109 pic16c745/765 13.6.1 int interrupt the external interrupt on rb0/int pin is edge trig- gered: either rising, if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie, decides whether or not the processor branches to the interrupt vector following wake-up. see section 13.9 for details on sleep mode. 13.6.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). (section 6.0) 13.6.3 portb interrupt on change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<3>) (section 5.2). 13.7 context saving during interrupts during an interrupt, only the pc is saved on the stack. at the very least, w and status should be saved to preserve the context for the interrupted program. all registers that may be corrupted by the isr, such as pclath or fsr, should be saved. example 13-1 stores and restores the status, w and pclath registers. the register, w_temp, is defined in common ram, the last 16 bytes of each bank that may be accessed from any bank. the status_temp and pclath_temp are defined in bank 0. the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register in bank 0. d) executes the isr code. e) restores the pclath register. f) restores the status register g) restores w. note that w_temp, status_temp and pclath_temp are defined in the common ram area (70h - 7fh) to avoid register bank switching during con- text save and restore. example 13-1: saving status, w, and pclath registers in ram #define w_temp 0x70 #define status_temp 0x71 #define pclath_temp 0x72 org 0x04 ; start at interrupt vector movwf w_temp ; save w register movf status,w movwf status_temp ; save status movf pclath,w movwf pclath_temp ; save pclath : (interrupt service routine) : movf pclath_temp,w movwf pclath movf status_temp,w movwf status swapf w_temp,f ; swapf w_temp,w ; swapf loads w without affecting status flags retfie note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt flag may not get set. 745cov.book page 109 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 110 preliminary ? 2000 microchip technology inc. 13.8 watchdog timer (wdt) the watchdog timer is a free running on-chip dedi- cated oscillator, which does not require any external components. the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and resume normal operation (watchdog timer wake-up). the wdt can be permanently disabled by clearing configuration bit wdte (section 13.1). 13.8.1 wdt period the wdt has a nominal time-out period of 18 ms (parameter #31, t wdt ). the time-out periods vary with temperature, v dd and process variations. if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option register. time-out periods up to 128 t wdt can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt. in addition, the sleep instruction prevents the wdt from generat- ing a reset, but will allow the wdt to wake the device from sleep mode. the to bit in the status register will be cleared upon a wdt time-out. 13.8.2 wdt programming considerations it should also be taken into account that under worst case conditions (v dd = min., temperature = max., and max. wdt prescaler), it may take several seconds before a wdt time-out occurs. figure 13-7: watchdog timer block diagram table 13-8: summary of watchdog timer registers note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 2007h config. bits ? boden (1) cp1 cp0 pwrte (1) wdte pll fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded cells are not used by the watchdog timer. note 1: see register 13-1 for operation of these bits. from tmr0 clock source (figure 6-1) to t m r 0 m u x (figure 6-1) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps<2:0> 0 1 mux psa wdt time-out note: psa and ps<2:0> are bits in the option register. 8 745cov.book page 110 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 111 pic16c745/765 13.9 power- d own mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the wdt will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (sta- tus<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 13.9.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a ? wake-up ? . the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. usb interrupt. 3. ccp capture mode interrupt. 4. parallel slave port read or write (pic16c765 only). 5. a/d conversion (when a/d clock source is dedi- cated internal oscillator). 6. usart tx or rx (synchronous slave mode). other peripherals cannot generate interrupts, since during sleep, no on-chip q clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 13.9.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bit will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction. 745cov.book page 111 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 112 preliminary ? 2000 microchip technology inc. figure 13-8: wake-up from sleep through interrupt 13.10 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 13.11 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the four least significant bits of the id location are used. 13.12 in-circuit serial programming pic16cxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware, or a custom firm- ware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low, while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/ verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c6x/7x programming specifications (literature #ds30228). figure 13-9: typical in-circuit serial programming connection q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: hs oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay is not present in ec osc mode. 3: gie = ? 1 ? assumed. after wake-up, the processor jumps to the interrupt routine. if gie = ? 0 ? , execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip does not recommend code pro- tecting windowed devices. devices that are code protected may be erased, but not pro- grammed again. external connector signals to n orm al connections to n orm al connections pic16cxx v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd 745cov.book page 112 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 113 pic16c745/765 14.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the pic16cxx instruction set summary in table 14-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 14-1 shows the opcode field descriptions. for byte-oriented instructions, ? f ? represents a file reg- ister designator and ? d ? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator which selects the number of the bit affected by the operation, while ? f ? represents the number of the file in which the bit is located. for literal and control operations, ? k ? represents an eight or eleven bit constant or literal value. table 14-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 s. table 14-2 lists the instructions recognized by the mpasm assembler. figure 14-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 14-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don ? t care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of i talics user defined term (font is courier) note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only 745cov.book page 113 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 114 preliminary ? 2000 microchip technology inc. table 14-2: pic16cxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023). 745cov.book page 114 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 115 pic16c745/765 14.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal ? k ? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ? f ? . if ? d ? is 0, the result is stored in the w register. if ? d ? is 1, the result is stored back in reg- ister ? f ? . andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and ? ed with the eight bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit 'b' in register 'f' is set. 745cov.book page 115 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 116 preliminary ? 2000 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ? b ? in register ? f ? is ? 0 ? , the next instruction is executed. if bit ? b ? is ? 1 ? , then the next instruc- tion is discarded and a nop is exe- cuted instead making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ? b ? in register ? f ? is ? 1 ? , the next instruction is executed. if bit ? b ? , in register ? f ? , is ? 0 ? , the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ? f ? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. 745cov.book page 116 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 117 pic16c745/765 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ? f ? are complemented. if ? d ? is 0, the result is stored in w. if ? d ? is 1, the result is stored back in register ? f ? . decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ? f ? . if ? d ? is 0, the result is stored in the w regis- ter. if ? d ? is 1, the result is stored back in register ? f ? . decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ? f ? are decremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . if the result is 1, the next instruc- tion is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in regis- ter ? f ? . if the result is 1, the next instruc- tion is executed. if the result is 0, a nop is executed instead making it a 2t cy instruction. 745cov.book page 117 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 118 preliminary ? 2000 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or ? ed with the eight bit literal 'k'. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in regis- ter 'f'. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register f are moved to a destination dependent upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight bit literal 'k' is loaded into w register. the don ? t cares will assemble as 0 ? s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to reg- ister 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. 745cov.book page 118 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 119 pic16c745/765 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight bit literal ? k ? . the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ? f ? are rotated one bit to the left through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is stored back in register ? f ? . rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ? f ? are rotated one bit to the right through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in reg- ister ? f ? . sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 13.9 for more details. register f c register f c 745cov.book page 119 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 120 preliminary ? 2000 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2 ? s complement method) from the eight bit literal 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2 ? s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w regis- ter. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor ? ed with the eight bit lit- eral 'k'. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. 745cov.book page 120 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 121 pic16c745/765 15.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian simulators - mplab-sim software simulator emulators - mplab-ice real-time in-circuit emulator - icepic ? in-circuit debugger - mplab-icd for pic16f87x device programmers -pro mate ? ii universal programmer - picstart ? plus entry-level prototype programmer low-cost demonstration boards -picdem-1 -picdem-2 -picdem-3 -picdem-17 -k ee l oq ? 15.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows ? -based applica- tion which contains: multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) a full featured editor a project manager customizable tool bar and key mapping a status bar on-line help mplab allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) debug using: - source files - absolute listing file - object code the ability to use mplab with microchip ? s simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 15.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcu ? s. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a stand-alone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: mpasm and mplink are integrated into mplab projects. mpasm allows user defined macros to be created for streamlined assembly. mpasm allows conditional assembly for multi pur- pose source files. mpasm directives allow complete control over the assembly process. 15.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi ? c ? compilers and inte- grated development environments for microchip ? s pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display. 745cov.book page 121 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 122 preliminary ? 2000 microchip technology inc. 15.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: mplink works with mpasm and mplab-c17 and mplab-c18. mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: mplib makes linking easier because single librar- ies can be included instead of many smaller files. mplib helps keep code maintainable by grouping related modules together. mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 15.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 15.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, ? make ? and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive development tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice is available in two versions; mplab-ice 1000 and mplab-ice 2000. mplab-ice 1000 is a basic, low-cost emulator system with simple trace capabilities. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. both systems use the same pro- cessor modules and will operate across the full operat- ing speed range of the picmicro mcu. 15.7 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchange- able personality modules or daughter boards. the emulator is capable of emulating without target applica- tion circuitry being present. 15.8 mplab-icd in-circuit debugger microchip ? s in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family. 745cov.book page 122 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 123 pic16c745/765 15.9 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 15.10 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 15.11 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchip ? s microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and downl oad the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 15.12 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 15.13 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 745cov.book page 123 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 124 preliminary ? 2000 microchip technology inc. 15.14 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 15.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. 745cov.book page 124 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 125 pic16c745/765 table 15-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ? -ice ** icepic ? low-cost in-circuit emulator debugger mplab ? -icd in-circuit debugger * * programmers picstart ? plus low-cost universal dev. kit ** pro mate ? ii universal programmer ** demo boards and eval kits picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid? programmer ? s kit 125 khz microid developer ? s kit 125 khz anticollision microid developer ? s kit 13.56 mhz anticollision microid developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? -icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c745/765 ds41124c-page 126 preliminary ? 2000 microchip technology inc. notes: 745cov.book page 126 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 127 pic16c745/765 16.0 electrical characteristics absolute maximum ratings ( ? ) ambient temperature under bias................................................................................................. ............-55 c to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr and ra4) .......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss .................................................................................................. -0.3v to +13.25v voltage on ra4 with respect to vss ............................................................................................. ............ -0.3v to +10.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (note 2) (combined) ...................................................200 ma maximum current sourced by porta, portb, and porte (note 2) (combined)..............................................200 ma maximum current sunk by portc and portd (note 2) (combined)..................................................................200 ma maximum current sourced by portc and portd (note 2) (combined).............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) 2: portd and porte not available on the pic16c745. ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operati on list- ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliabi lity. 745cov.book page 127 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 128 preliminary ? 2000 microchip technology inc. figure 16-1: valid operating regions, frequency on f int , -40 c ta +85 c frequency voltage 5.5 v 5.25 v 24 mhz 4.35 v 4.0 v 745cov.book page 128 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 129 pic16c745/765 16.1 dc characteristics: p ic16c745/765 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 cfor industrial param no. sym characteristic min typ ? max units conditions d001 v dd supply voltage 4.35 ? 5.25 v see figure 16-1 d002* v dr ram data retention voltage (note 1) ? 1.5 ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? v ss ? v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd ? ? ? ? v/ms v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 ? 4.35 v brown-out reset is always active d010 d013 i dd supply current (note 2, 4) ? ? 14 18 16 20 ma ma f int = 24 mhz, v dd = 4.35v f int = 24 mhz, v dd = 5.25v d020 d021 d021b i pd power-down current (note 3, 4) ? ? 90 100 120 140 a a v dd = 4.35v w/ usb suspended v dd = 5.25v w/ usb suspended d022* d022a* ? i wdt ? i usb ? pll module differential current (note 5, 6) watchdog timer not suspend mode phase lock loop ? ? ? 6.0 40 1.5 20 180 3.0 a a ma wdte bit set, v dd = 4.35v wdte bit set, v dd = 4.35v wdte bit set, v dd = 4.35v 1a f osc hs oscillator operating freq. h4 oscillator operating freg. ec oscillator operating freq. e4 oscillator operating freq. 24 6 24 6 ? ? ? ? 24 6 24 6 mhz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 5: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 6: module differential currents measured at f int = 24 mhz. 745cov.book page 129 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 130 preliminary ? 2000 microchip technology inc. 16.2 dc characteristics: pic16c745/765 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial operating voltage v dd range as described in dc spec section 16.1 and section 16.2 param no. sym characteristic min typ ? max units conditions input low voltage v il i/o ports d030 d030a with ttl buffer v ss ? 0.8 v d031 with schmitt trigger buffer v ss ? 0.2 v dd v for entire v dd range d032 mclr , osc1 (in ec, e4 mode) v ss ? 0.2 v dd v d033 osc1 (in hs, h4 mode) v ss ? 0.3 v dd v note 1 input high voltage v ih i/o ports ? d040 with ttl buffer 2.0 ? v dd v d041 with schmitt trigger buffer 0.8 v dd ? v dd v for entire v dd range d042 mclr 0.8 v dd ? v dd v d042a osc1 (hs, h4 mode) 0.7 v dd ? v dd v note 1 d043 osc1 (in ec, e4 mode) 0.9 v dd ? v dd v input leakage current (notes 2, 3) d060 i il i/o ports ?? 1 av ss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki ?? 5 av ss v pin v dd d063 osc1 ?? 5 av ss v pin v dd , hs osc mode d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss a vih a voh a vil a vol d+ in d- in d+ out d- out d+ in d- in d+ out d- out 2.4 2.4 2.8 2.8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3.6 3.6 .8 .8 .3 .3 v v v v v v v v v dd = 4.35v w/ usb suspended (note 4) v dd = 4.35v w/ usb suspended v dd = 4.35v w/ usb suspended (note 4) v dd = 4.35v w/ usb suspended v dd = 4.35v w/ usb suspended (note 4) v dd = 4.35v w/ usb suspended v dd = 4.35v w/ usb suspended (note 4) v dd = 4.35v w/ usb suspended output low voltage d080 v ol i/o ports ?? 0.6 v i ol = 8.5 ma, v dd = 4.35v, -40 c to +85 c d083 osc2/clkout (ec, e4 osc mode) ?? 0.6 v i ol = 1.6 ma, v dd = 4.35v, -40 c to +85 c output high voltage d090 v oh i/o ports (note 3) v dd -0.7 ?? vi oh = -3.0 ma, v dd = 4.35v, -40 c to +85 c d092 osc2/clkout (ec osc mode) v dd -0.7 ?? vi oh = -1.3 ma, v dd = 4.35v, -40 c to +85 c d150* v od open-drain high voltage ?? 10.5 v ra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin ?? 15 pf in hs mode when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in ec mode) ?? 50 pf c vusb v usb regulation capacitor ? 200 ? nf + 20% (see section 10.7.1) *these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in ec oscillator mode, the osc1/clkin pin is a schmitt trigger input. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameters are per usb specification 1.1. no microchip specific parameter numbers exist (per the picmicro ? mid-range reference manual, ds33023. 745cov.book page 130 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 131 pic16c745/765 16.3 a c (timing) characteristics 16.3.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod h high r rise i invalid (hi-impedance) v valid l low z hi-impedance 745cov.book page 131 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 132 preliminary ? 2000 microchip technology inc. 16.3.2 timing conditions the temperature and voltages specified in table 16-1 apply to all timing specifications unless otherwise noted. figure 16-2 specifies the load conditions for the timing specifications. table 16-1: temperature and voltage specifications - ac figure 16-2: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial operating voltage v dd range as described in dc spec section 16.1 and section 16.2. v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2/clkout, but including d and e (1) outputs as ports c l = 15 pf for osc2 output load condition 1 load condition 2 note 1: pic16c765 only. 745cov.book page 132 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 133 pic16c745/765 16.3.3 timing diagrams and specifications figure 16-3: external clock timing figure 16-4: clock multiplier (pll) phase relationship 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout f int osc1/ clkin note 1: f int represents the internal clock signal. f int equals f osc or clkin if the pll is disabled. f int equals 4x f osc or 4x clkin if the pll is enabled. t cy is always 4/f int . f int is osc1 pin in ec mode, pll disabled. 2: f int = osc1 in ec mode with pll disabled. 745cov.book page 133 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 134 preliminary ? 2000 microchip technology inc. table 16-2: external clock timing requirements param no. sym characteristic min typ ? max units conditions 1a f osc external clkin frequency (note 1) 24 ? 24 mhz ec osc mode 6 ? 6 mhz e4 osc mode oscillator frequency (note 1) 24 ? 24 mhz hs osc mode 6 ? 6 mhz h4 osc mode 1t osc external clkin period (note 1) 41 ? 41 ns ec osc modes 167 ? 167 ns e4 osc mode oscillator period (note 1) 41 ? 41 ns hs osc modes 167 ? 167 ns h4 osc mode 2t cy instruction cycle time (note 1) 167 ? dc ns t cy = 4/f int 3* t os l, t os h external clock in (osc1) high or low time 10 ?? ns ec oscillator 4* t os r, t os f external clock in (osc1) rise or fall time ?? 15 ns ec oscillator * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period when the pll is enabled, or the input oscillator time-base period divided by 4 when the pll is disabled. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ? min. ? values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the ? max. ? cycle time limit is ? dc ? (no clock) for all devices. 745cov.book page 134 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 135 pic16c745/765 figure 16-5: clkout and i/o timing table 16-3: clkout and i/o timing requirements param no. sym characteristic min typ ? max units conditions 10* t os h2 ck losc1 to clkout ? 75 200 ns note 1 11* t os h2 ck hosc1 to clkout ? 75 200 ns note 1 12* t ck r clkout rise time ? 35 100 ns note 1 13* t ck f clkout fall time ? 35 100 ns note 1 14* t ck l2 io vclkout to port out valid ?? 0.5 t cy + 20 ns note 1 15* t io v2 ck h port in valid before clkout t osc + 200 ?? ns note 1 16* t ck h2 io i port in hold after clkout 0 ?? ns note 1 17* t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18* t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) 100 ?? ns 19* t io v2 os h port input valid to osc1 (i/o in setup time) 0 ?? ns 20* t io r port output rise time ? 10 40 ns 21* t io f port output fall time ? 10 40 ns 22 ?? *t inp int pin high or low time t cy ?? ns 23 ?? *t rbp rb<7:4> change int high or low time t cy ?? ns * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in ec mode where clkout output is 4 x t osc . 2: f int = osc1 when pll is disabled. note : refer to figure 16-2 for load conditions. f int clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value 745cov.book page 135 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 136 preliminary ? 2000 microchip technology inc. figure 16-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 16-7: brown-out reset timing table 16-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements param no. sym characteristic min typ ? max units conditions 30 t mc lmclr pulse width (low) 2 ?? sv dd = 5v, -40 c to +85 c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40 c to +85 c 32 t ost oscillation start-up timer period ? 1024 t osc ?? t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40 c to +85 c 34 t ioz i/o hi-impedance from mclr low or wdt reset ?? 2.1 s 35 t bor brown-out reset pulse width 100 ?? sv dd b vdd (d005) 36 t pllrt pll settling time period ? 1.4 ? ms t osc = osc1 period * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 16-2 for load conditions. v dd bv dd 35 745cov.book page 136 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 137 pic16c745/765 figure 16-8: timer0 and timer1 external clock timings table 16-5: timer0 and timer1 external clock requirements note: refer to figure 16-2 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1 param no. sym characteristic min typ ? max units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 42* t t 0p t0cki period no prescaler t cy + 40 ?? ns n = prescale value (2, 4,..., 256) with prescaler greater of: 20 or t cy + 40 n ?? ns 45* t t 1h t1cki high time synchronous, prescaler = 1 0.5 t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 15 ?? ns asynchronous 30 ?? ns 46* t t 1l t1cki low time synchronous, prescaler = 1 0.5 t cy + 20 ?? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 15 ?? ns asynchronous 30 ?? ns 47* t t 1p t1cki input period synchronous greater of : 30 or t cy + 40 n ?? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ?? ns f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200 khz 48 tckez tmr 1 delay from external clock edge to timer increment 2tosc ? 7tosc ? * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 745cov.book page 137 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 138 preliminary ? 2000 microchip technology inc. figure 16-9: capture/compare/pwm timings (ccp1 and ccp2) table 16-6: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 16-2 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. sym characteristic min typ ? max units conditions 50* t cc l ccp1 and ccp2 input low time no prescaler 0.5 t cy + 20 ?? ns with prescaler 10 ?? ns 51* t cc h ccp1 and ccp2 input high time no prescaler 0.5 t cy + 20 ?? ns with prescaler 10 ?? ns 52* t cc p ccp1 and ccp2 input period 3 t cy + 40 n ?? ns n = prescale value (1,4, or 16) 53* t cc r ccp1 and ccp2 output rise time ? 10 25 ns 54* t cc f ccp1 and ccp2 output fall time ? 10 25 ns * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 745cov.book page 138 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 139 pic16c745/765 figure 16-10: parallel slave port timing (pic16c765) table 16-7: parallel slave port requirements note : refer to figure 16-2 for load conditions. re2/cs re0/rd re1/wr rd<7:0> 62 63 64 65 param no. sym characteristic min typ ? max units conditions 62* t dt v2 wr h data in valid before wr or cs (setup time) 20 ?? ns 63* t wr h2 dt iwr or cs to data ? in invalid (hold time) 20 ?? ns 64 t rd l2 dt vrd and cs to data ? out valid ?? 80 ns 65* t rd h2 dt ird or cs to data ? out invalid 10 ? 30 ns *these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: pic16c765 only. 745cov.book page 139 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 140 preliminary ? 2000 microchip technology inc. figure 16-11: usart synchronous transmission (master/slave) timing table 16-8: usart synchronous transmission requirements figure 16-12: usart synchronous receive (master/slave) timing table 16-9: usart synchronous receive requirements param no. sym characteristic min typ ? max units conditions 120* t ck h2 dt v sync xmit (master & slave) clock high to data out valid ?? 80 ns 121* t ckrf clock out rise time and fall time (master mode) ?? 45 ns 122* t dtrf data out rise time and fall time ?? 45 ns *these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. param no. sym characteristic min typ ? max units conditions 125* t dt v2 ck l sync rcv (master & slave) data setup before ck (dt setup time) 15 ?? ns 126* t ck l2 dtl data hold after ck (dt hold time) 15 ?? ns *these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 16-2 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note : refer to figure 16-2 for load conditions. 125 126 rc6/tx/ck pin rc7/rx/dt pin 745cov.book page 140 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 141 pic16c745/765 table 16-10: a/d converter characteristics: pic16c745/765 (industrial) param no. sym characteristic min typ ? max units conditions a01 n r resolution ?? 8 bits bit a02 e abs total absolute error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ?? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity (note 3) ? warranteed ?? v ss v ain v ref a20 v ref reference voltage 2.5v ? v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 ? v ref + 0.3 v a30 z ain recommended impedance of analog voltage source ?? 10.0 k ? a40 i ad a/d conversion current (v dd ) ? 180 ? a average current consump- tion when a/d is on (note 1) a50 i ref v ref input current (note 2) 10 ? ? ? 1000 10 a a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 12.1. during a/d conversion cycle * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from the ra3 pin or the v dd pin, whichever is selected as a reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 745cov.book page 141 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 142 preliminary ? 2000 microchip technology inc. figure 16-13: a/d conversion timing table 16-11: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 76543210 note: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134 param no. sym characteristic min typ ? max units conditions 130 t ad a/d clock period 1.6 ?? st osc based, v ref 3.0v 2.0 ?? st osc based, 2.5v v ref 5.5v 2.0 4.0 6.0 sa/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 ? 11 t ad 132 t acq acquisition time 5* ?? s the minimum time is the ampli- fier settling time. this may be used if the ? new ? input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ?? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert sample time 1.5 ?? t ad * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 12.1 for minimum conditions. 745cov.book page 142 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 143 pic16c745/765 figure 16-14: maximum input waveform timing specifications figure 16-15: usb low speed signaling table 16-12: usb ac and dc specifications note 1: the d+/d- signals can withstand a continuous short to v bus , gnd, cable shield or any other signal. 66.7ns 6mhz 4.6v 60ns -1.0v 4ns min 20ns max 4ns min 20ns max min pin r src r src = 39 ? 2% v 72 70 10% 90% data differential lines 71 90% 10% note 1: parameters are per usb specification 1.1. no microchip specific parameter numbers exist (per the picmicro ? mid-range reference manual, ds33023. parameter no. sym characteristic min t yp ? max units conditions t lr transition rise time 75 300 ns (note 1) t lf transition fall time 75 300 ns (note 1) v crs crossover voltage 1.3 2.0 v (note 1) t lrfm rise and fall time matching 80 125 % (note 1) v il voltage input low 0.8 v (note 1) v ih voltage input high 2.0 v (note 1) v ihz voltage input high floating 2.7 3.6 v (note 1) differential input sensitivity 0.2 v (d+)-(d-) (note 1) differential common mode range 0.8 2.5 v (note 1) v ol voltage output low 0.0 0.3 v (note 1) v oh voltage output high 2.8 3.6 v (note 1) v usb usb voltage output 2.7 3.6 v i usb = 0 to 230 a in suspend mode 0 to 2.6ma in non-suspend mode (note 1) note 1: parameters are per usb specification 1.1. no microchip specific parameter numbers exist (per the picmicro ? mid-range reference manual, ds33023. 745cov.book page 143 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 144 preliminary ? 2000 microchip technology inc. notes: 745cov.book page 144 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 145 pic16c745/765 17.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables, the data presented are outside specified operating range. this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ? typical ? represents the mean of the distribution. figure 17-1: typical i dd vs. v dd (f int = 24mhz) figure 17-2: typical i pd vs. v dd (usb suspended, wdt disabled) i dd (ma) v dd (v) 25.00 20.00 15.00 10.00 5.00 4.35 5.00 5.25 - 4 0 c 2 5 c 85 c v dd (v) 160.00 140.00 120.00 100.00 80.00 4.35 5.00 5.25 - 4 0 c 2 5 c 8 5 c i pd ( a) 745cov.book page 145 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 146 preliminary ? 2000 microchip technology inc. figure 17-3: dc load lines for usb regulator output (v usb ) regulation voltage (v) load current (ma) 4 3 2 1 0 -1 -2 0 5 10 15 20 25 30 35 40 45 - 4 0 c 2 5 c 8 5 c 745cov.book page 146 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 147 pic16c745/765 18.0 packaging information 18.1 package marking information 28-lead soic xxxxxxxxxxxxxxxxxxxx yywwnnn example PIC16C745-I/so yywwnnn 28-lead pdip (skinny dip) example PIC16C745-I/sp 9917017 9917017 * standard otp marking consists of microchip part number, year code, week code and traceability code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. xxxxxxxxxx yywwnnn 28-lead side braze windowed (jw) PIC16C745-I/jw example 9905017 xxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx 745cov.book page 147 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 148 preliminary ? 2000 microchip technology inc. package marking information (cont ? d) xxxxxxxxxxxxxxxxxx yywwnnn 40-lead pdip example pic16c765-i/p 9917017 44-lead tqfp xxxxxxxxxx yywwnnn xxxxxxxxxx example 44-lead plcc example xxxxxxxxxxxxxxxxxx xxxxxxxxxx xxxxxxxxxxx yywwnnn 40-lead cerdip windowed PIC16C745-I/jw example 9905017 xxxxxxxxxxx xxxxxxxxxxx xxxxxxxxxxxxxxxxxx pic16c765-i/pt 9917017 xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx pic16c765-i/l 9917017 745cov.book page 148 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 149 pic16c745/765 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. significant characteristic 745cov.book page 149 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 150 preliminary ? 2000 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic 745cov.book page 150 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 151 pic16c745/765 28-lead ceramic side brazed dual in-line with window (jw) ? 300 mil 7.49 7.24 6.99 .295 .285 .275 u lid width 12.95 12.70 12.45 .510 .500 .490 t lid length 4.34 4.22 4.09 .171 .166 .161 w window diameter 8.23 7.87 7.52 .324 .310 .296 eb overall row spacing 0.51 0.46 0.41 .020 .018 .016 b lower lead width 1.32 1.27 1.22 .052 .050 .048 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.56 3.30 .150 .140 .130 l tip to seating plane 35.92 35.56 35.20 1.414 1.400 1.386 d overall length 7.62 7.37 7.11 .300 .290 .280 e1 package width 1.52 1.27 1.02 .060 .050 .040 a1 standoff 3.94 3.43 2.92 .155 .135 .115 a2 top of body to seating plane 5.03 4.48 3.94 .198 .177 .155 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units c eb 2 1 d n t w u e1 p a2 l a1 a b1 b * controlling parameter significant characteristic jedec equivalent: ms-015 drawing no. c04-084 745cov.book page 151 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 152 preliminary ? 2000 microchip technology inc. 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic 745cov.book page 152 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 153 pic16c745/765 40-lead ceramic dual in-line with window (jw) ? 600 mil (cerdip) 9.14 8.89 8.64 .360 .350 .340 w window diameter 18.03 16.76 15.49 .710 .660 .610 eb overall row spacing 0.58 0.51 0.41 .023 .020 .016 b1 lower lead width 1.40 1.33 1.27 .055 .053 .050 b upper lead width 0.36 0.28 0.20 .014 .011 .008 c lead thickness 3.68 3.56 3.43 .145 .140 .135 l tip to seating plane 52.32 52.07 51.82 2.060 2.050 2.040 d overall length 13.36 13.21 13.06 .526 .520 .514 e1 ceramic pkg. width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 1.52 1.14 0.76 .060 .045 .030 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 5.72 5.21 4.70 .225 .205 .185 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n c eb e p l b1 b a2 * controlling parameter significant characteristic jedec equivalent: mo-103 drawing no. c04-014 745cov.book page 153 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 154 preliminary ? 2000 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 ch x 45 significant characteristic 745cov.book page 154 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 155 pic16c745/765 44-lead plastic leaded chip carrier (l) ? square (plcc) ch2 x 45 ch1 x 45 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 11 11 n1 pins per side 16.00 15.75 14.99 .630 .620 .590 d2 footprint length 16.00 15.75 14.99 .630 .620 .590 e2 footprint width 16.66 16.59 16.51 .656 .653 .650 d1 molded package length 16.66 16.59 16.51 .656 .653 .650 e1 molded package width 17.65 17.53 17.40 .695 .690 .685 d overall length 17.65 17.53 17.40 .695 .690 .685 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p a3 a 35 b1 b d2 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 lower lead width * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-048 significant characteristic 745cov.book page 155 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 156 preliminary ? 2000 microchip technology inc. notes: 745cov.book page 156 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 157 pic16c745/765 index a a/d adcon0 register ..................................................... 91 analog input model block diagram ........................... 95 analog-to-digital converter ....................................... 91 block diagram ........................................................... 94 configuring analog port pins .................................... 96 configuring the interrupt ............................................ 94 configuring the module ............................................. 94 conversion clock ...................................................... 96 conversions .............................................................. 96 converter characteristics ........................................ 141 effects of a reset ...................................................... 96 faster conversion - lower resolution tradeoff ........ 96 internal sampling switch (rss) impedance ................ 95 operation during sleep ............................................. 96 sampling requirements ............................................ 95 source impedance .................................................... 95 timing diagram ....................................................... 142 using the ccp trigger .............................................. 97 absolute maximum ratings ............................................. 127 adres register ......................................................... 17 , 91 application notes an552 (implementing wake-up on key strokes using pic16cxxx) ................................................... 33 an556 (table reading using pic16cxx ................. 29 an607, power-up trouble shooting ........................ 103 architecture overview ..................................................................... 9 assembler mpasm assembler ................................................. 121 b baud rate formula ........................................................... 79 block diagrams a/d ............................................................................ 94 analog input model ................................................... 95 capture ...................................................................... 53 compare .................................................................... 54 on-chip reset circuit ............................................. 102 portc ...................................................................... 35 portd (in i/o port mode) ........................................ 37 portd and porte as a parallel slave port ........... 40 porte (in i/o port mode) ........................................ 38 pwm .......................................................................... 54 ra4/t0cki pin .......................................................... 31 rb port pins .............................................................. 33 rb port pins .............................................................. 33 timer0/wdt prescaler .............................................. 43 timer2 ....................................................................... 49 usart receive ........................................................ 83 usart transmit ....................................................... 81 watchdog timer ...................................................... 110 bor bit ............................................................................ 103 brgh bit ........................................................................... 79 brown-out reset (bor) timing diagram ....................................................... 136 buffer descriptor table ...................................................... 68 c c bit ................................................................................... 22 capture/compare/pwm capture block diagram ................................................... 53 ccp1con register .......................................... 52 ccp1if ............................................................. 53 mode ................................................................. 53 prescaler ........................................................... 53 ccp timer resources .............................................. 51 compare block diagram ................................................... 54 mode ................................................................. 54 software interrupt mode ................................... 54 special event trigger ........................................ 54 special trigger output of ccp1 ....................... 54 special trigger output of ccp2 ....................... 54 interaction of two ccp modules .............................. 51 section ...................................................................... 51 special event trigger and a/d conversions ............. 54 capture/compare/pwm (ccp) pwm block diagram ................................................. 54 pwm mode ............................................................... 54 timing diagram ....................................................... 138 ccp1con ......................................................................... 19 ccp2con ......................................................................... 19 ccpr1h register ............................................... 17 , 19 , 51 ccpr1l register ....................................................... 19 , 51 ccpr2h register ...................................................... 17 , 19 ccpr2l register ....................................................... 17 , 19 clocking scheme .............................................................. 13 code examples call of a subroutine in page 1 from page 0 .............. 29 changing prescaler (timer0 to wdt) ....................... 44 indirect addressing ................................................... 30 initializing porta ..................................................... 31 code protection ....................................................... 99 , 112 computed goto .............................................................. 29 configuration bits .............................................................. 99 control ............................................................................... 60 cren bit ........................................................................... 78 cs pin ............................................................................... 40 d dc bit ................................................................................ 22 dc characteristics ................................................. 129 , 130 development support ................................................ 5 , 121 direct addressing .............................................................. 30 e ec oscillator ................................................................... 104 electrical characteristics ................................................. 127 endpoint ............................................................................ 71 errata .................................................................................. 3 error .................................................................................. 63 f ferr bit ............................................................................ 78 fsr register ................................................ 17 , 18 , 20 , 30 g general description ............................................................ 5 gie bit ............................................................................. 107 745cov.book page 157 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 158 preliminary ? 2000 microchip technology inc. i i/o ports ............................................................................ 31 porta ...................................................................... 31 portb ...................................................................... 33 portc ...................................................................... 35 portd ............................................................... 37 , 40 porte ...................................................................... 38 in-circuit serial programming .................................. 99 , 112 indf ........................................................................... 19 , 20 indf register ...................................................... 17 , 18 , 30 indirect addressing ............................................................ 30 instruction cycle ................................................................ 13 instruction flow/pipelining ................................................. 13 instruction format ............................................................ 113 instruction set addlw .................................................................... 115 addwf ................................................................... 115 andlw .................................................................... 115 andwf ................................................................... 115 bcf ......................................................................... 115 bsf .......................................................................... 115 btfsc ..................................................................... 116 btfss ..................................................................... 116 call ........................................................................ 116 clrf ....................................................................... 116 clrw ...................................................................... 116 clrwdt ................................................................. 116 comf ...................................................................... 117 decf ....................................................................... 117 decfsz .................................................................. 117 goto ...................................................................... 117 incf ........................................................................ 117 incfsz .................................................................... 117 iorlw ..................................................................... 118 iorwf ..................................................................... 118 movf ...................................................................... 118 movlw ................................................................... 118 movwf ................................................................... 118 nop ......................................................................... 118 retfie .................................................................... 119 retlw .................................................................... 119 return .................................................................. 119 rlf .......................................................................... 119 rrf ......................................................................... 119 sleep ..................................................................... 119 sublw 1.................................................................... 20 subwf .................................................................... 120 swapf .................................................................... 120 xorlw ................................................................... 120 xorwf ................................................................... 120 summary table ....................................................... 114 instruction set summary ................................................. 113 int interrupt .................................................................... 109 intcon ............................................................................. 20 intcon register .............................................................. 24 intedg bit ...................................................................... 109 internal sampling switch (rss) impedance ....................... 95 interrupts .................................................................. 99 , 107 portb change .......................................................... 109 rb port change ........................................................ 33 tmr0 ....................................................................... 109 irp bit ................................................................................ 22 k keeloq ? evaluation and programming tools ................ 124 l loading of pc ................................................................... 29 m mclr ..................................................................... 101 , 104 memory data memory ............................................................. 15 program memory ...................................................... 15 program memory maps pic16c745/765 ................................................ 15 mplab integrated development environment software ..................................................... 121 o oerr bit ........................................................................... 78 opcode ......................................................................... 113 option register .............................................................. 23 osc selection ................................................................... 99 oscillator e4 ............................................................................ 100 ec ........................................................................... 100 h4 ............................................................................ 100 hs .................................................................. 100 , 104 oscillator configurations ................................................. 100 p packaging ....................................................................... 147 paging, program memory ................................................. 29 parallel slave port ...................................................... 37 , 40 parallel slave port (psp) timing diagram ....................................................... 139 pcl register ....................................................... 17 , 18 , 29 pclath .......................................................................... 105 pclath register ......................................... 17 , 18 , 20 , 29 pcon register ......................................................... 28 , 103 pd bit ....................................................................... 22 , 101 picdem-1 low-cost picmicro demo board .................. 123 picdem-2 low-cost pic16cxx demo board ............... 123 picdem-3 low-cost pic16cxxx demo board ............. 123 picstart ? plus entry level development system ..... 123 pie1 register .................................................................... 25 pie2 register .................................................................... 27 pinout descriptions pic16c745/765 ......................................................... 11 pir1 register .................................................................... 26 pir2 register .................................................................... 27 pop ................................................................................... 29 por ................................................................................ 103 oscillator start-up timer (ost) ....................... 99 , 103 power control register (pcon) ............................. 103 power-on reset (por) ........................... 99 , 103 , 105 power-up timer (pwrt) ........................................... 99 power-up-timer (pwrt) ........................................ 103 to ........................................................................... 101 por bit ............................................................................ 103 port rb interrupt ............................................................. 109 porta ..................................................................... 20 , 105 porta register ......................................................... 17 , 31 portb ..................................................................... 20 , 105 portb register ......................................................... 17 , 33 portc ..................................................................... 20 , 105 portc register ........................................................ 17 , 35 portd ..................................................................... 20 , 105 portd register ........................................................ 17 , 37 porte ..................................................................... 20 , 105 porte register ......................................................... 17 , 38 power-down mode (sleep) ........................................... 111 745cov.book page 158 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 159 pic16c745/765 power-on reset (por) timing diagram ....................................................... 136 pr2 register .............................................................. 18 , 49 pro mate ? ii universal programmer ........................... 123 product identification system .......................................... 163 program counter pclath register .................................................... 109 program memory paging ....................................................................... 29 program memory maps pic16c745/765 ......................................................... 15 program verification ........................................................ 112 pspmode bit ...................................................... 37 , 38 , 40 push ................................................................................. 29 r rbif bit ..................................................................... 33 , 109 rcreg .............................................................................. 19 rcsta register ......................................................... 19 , 78 rd pin ................................................................................ 40 register file ...................................................................... 15 registers fsr summary ........................................................... 19 indf summary ........................................................... 19 intcon summary ........................................................... 19 pcl summary ........................................................... 19 pclath summary ........................................................... 19 portb summary ........................................................... 19 reset conditions ..................................................... 104 special function register summary ......................... 17 status summary ........................................................... 19 tmr0 summary ........................................................... 19 trisb summary ........................................................... 20 reset ........................................................................ 99 , 101 timing diagram ....................................................... 136 reset conditions for special registers ........................... 104 rp0 bit ........................................................................ 15 , 22 rp1 bit ............................................................................... 22 rx9 bit ............................................................................... 78 rx9d bit ............................................................................ 78 s serial communication interface (sci) module, see usart services one-time-programmable (otp) ................................. 7 quick-turnaround-production (qtp) .......................... 7 serialized quick-turnaround production (sqtp) ....... 7 sleep ...................................................................... 99 , 101 software simulator (mplab-sim) ................................... 122 spbrg register ................................................................ 18 special features of the cpu ............................................. 99 special function registers ................................................ 17 pic16c745/765 ......................................................... 17 spen bit ............................................................................ 78 sren bit ............................................................................ 78 sspbuf ............................................................................ 19 stack .................................................................................. 29 overflows .................................................................. 29 underflow .................................................................. 29 status ................................................................................ 64 status register ..................................................... 22 , 109 synchronous serial port module ....................................... 57 t t1ckps0 bit ..................................................................... 45 t1ckps1 bit ..................................................................... 45 t1con .............................................................................. 20 t1con register ......................................................... 19 , 45 t1oscen bit .................................................................... 45 t1sync bit ....................................................................... 45 t2ckps0 bit ..................................................................... 49 t2ckps1 bit ..................................................................... 49 t2con register ......................................................... 19 , 49 t ad .................................................................................... 96 timer0 rtcc ...................................................................... 105 timing diagram ....................................................... 137 timer1 timing diagram ....................................................... 137 timers timer0 ....................................................................... 43 external clock ................................................... 44 interrupt ............................................................. 43 prescaler ........................................................... 44 prescaler block diagram .................................. 43 t0cki ................................................................ 44 t0if ................................................................. 109 tmr0 interrupt ................................................ 109 timer1 asynchronous counter mode ........................... 47 capacitor selection ........................................... 47 operation in timer mode .................................. 46 oscillator ........................................................... 47 prescaler ........................................................... 47 resetting of timer1 registers .......................... 47 resetting timer1 using a ccp trigger output ................................................... 47 synchronized counter mode ............................ 46 t1con .............................................................. 45 tmr1h .............................................................. 47 tmr1l .............................................................. 47 timer2 block diagram ................................................... 49 module .............................................................. 49 postscaler ......................................................... 49 prescaler ........................................................... 49 t2con .............................................................. 49 timing diagrams usart asynchronous master transmission ............ 82 usart asynchronous reception ............................. 83 usart synchronous reception ............................... 88 usart synchronous transmission .......................... 86 wake-up from sleep via interrupt .................. 108 , 112 timing diagrams and specifications ............................... 133 a/d conversion ....................................................... 142 brown-out reset (bor) .......................................... 136 capture/compare/pwm (ccp) ............................... 138 clkout and i/o ..................................................... 135 external clock ......................................................... 133 oscillator start-up timer (ost) .............................. 136 parallel slave port (psp) ........................................ 139 power-up timer (pwrt) ......................................... 136 reset ....................................................................... 136 timer0 and timer1 .................................................. 137 usart synchronous receive (master/slave) ........ 140 745cov.book page 159 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 160 preliminary ? 2000 microchip technology inc. usart synchronous transmission (master/slave) ......................................................... 140 watchdog timer (wdt) ........................................... 136 tmr0 ................................................................................. 20 tmr0 register .................................................................. 17 tmr1cs bit ....................................................................... 45 tmr1h .............................................................................. 20 tmr1h register ................................................................ 17 tmr1l ............................................................................... 20 tmr1l register ................................................................ 17 tmr1on bit ....................................................................... 45 tmr2 ................................................................................. 20 tmr2 register .................................................................. 17 tmr2on bit ....................................................................... 49 to bit ................................................................................. 22 toutps0 bit ..................................................................... 49 toutps1 bit ..................................................................... 49 toutps2 bit ..................................................................... 49 toutps3 bit ..................................................................... 49 trisa register ........................................................... 18 , 31 trisb register ........................................................... 18 , 33 trisc register .......................................................... 18 , 35 trisd register .......................................................... 18 , 37 trise register .................................................... 18 , 38 , 39 txreg .............................................................................. 19 txsta register ................................................................. 77 u universal synchronous asynchronous receiver transmitter (usart) .......................................... 77 usart asynchronous mode .................................................. 81 asynchronous receiver ............................................. 83 asynchronous reception ........................................... 84 asynchronous transmitter ......................................... 81 baud rate generator (brg) ..................................... 79 receive block diagram ............................................. 83 sampling .................................................................... 79 synchronous master mode ........................................ 85 timing diagram, synchronous receive .......... 140 timing diagram, synchronous transmission .. 140 synchronous master reception ................................ 87 synchronous master transmission ........................... 85 synchronous slave mode .......................................... 89 synchronous slave reception .................................. 89 synchronous slave transmit ..................................... 89 transmit block diagram ............................................ 81 usb ....................................................... 21 , 58 , 60 , 61 , 62 usb address register ....................................................... 66 usb control register ........................................................ 65 usb endpoint control register ......................................... 67 uv erasable devices ........................................................... 7 w w register ...................................................................... 109 wake-up from sleep ..................................................... 111 watchdog timer (wdt) ......................... 99 , 101 , 104 , 110 timing diagram ....................................................... 136 wdt ................................................................................ 104 block diagram ......................................................... 110 period ...................................................................... 110 programming considerations .................................. 110 timeout ................................................................... 105 wr pin .............................................................................. 40 www, on-line support ...................................................... 3 z z bit ................................................................................... 22 745cov.book page 160 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 161 pic16c745/765 on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster, pro mate and mplab are reg- istered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom and fuzzy lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. 991103 745cov.book page 161 wednesday, august 2, 2000 8:24 am
pic16c745/765 ds41124c-page 162 preliminary ? 2000 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet.. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41124c pic16c745/765 745cov.book page 162 wednesday, august 2, 2000 8:24 am
? 2000 microchip technology inc. preliminary ds41124c-page 163 pic16c745/765 p r oduct id e n tification s y s t e m to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type. sales and support part no. x /xx xxx pattern package temperature range device device pic16c745 (1) , pic16c745t (2) pic16c765 (1) , pic16c765t (2) temperature range i = -40 c to +85 c(industrial) package jw = windowed cerdip - 600 mil pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip l=plcc pattern qtp code or special requirements (blank otherwise) examples: a) PIC16C745-I/p 301 = industrial temp., pdip package, qtp pattern #301. note 1: c= cmos note 2: t = in tape and reel - soic, plcc, tqfp, packages only. data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. 745cov.book page 163 wednesday, august 2, 2000 8:24 am
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 03/01/02 w orldwide s ales and s ervice

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